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CCS/66AK2E05: Allocate Bare metal application in DDR address space

Part Number: 66AK2E05
Other Parts Discussed in Thread: 66AK2G02

Tool/software: Code Composer Studio

Hi !

I try to built Hello World application for custom board based on 66AK2E05. I use this and this guides.

I use 66AK2G02.lds file with the following corrections:

MSMC_SRAM : o = 0x0C000000, l = 0x00100000 /* 1MB MSMC Shared SRAM */

MSMC_SRAM : o = 0x0C000000, l = 0x00200000 /* 2MB MSMC Shared SRAM */

DDR0 : o = 0x80000000, l = 0x80000000 /* 2GB external DDR0 */

DDR0 : o = 0x80000000, l = 0x40000000 /* 1GB external DDR0 */

When I allocate sections in MSMC_SRAM (in lds file):

 } > MSMC_SRAM

the application is executed correctly.

But when I allocate sections to DDR0:

 } > DDR0

the application causes an error at startup.

How do I correctly allocate the program in DDR memory?

ССS7.4. Win7 32bit.

DDR Memory is correctly initialized in GEL, ddr_memory_test script passed.

  • Hi,

    I don't have a K2E board, but unfortunately on my K2H board I was not able to reproduce this issue.

    The modifications you made look fine and the differences between DDR0 and MSMC should only be a problem if the memory is previously misconfigured (which does not seem to be your case) or something in the code causes it to go bad - a rather strange occurrence on a "hello" program.

    One detail you can try to pursue is to disable the Auto-Run to main() and see if you can single-step the code from the Entry point to main.

    To disable this, please check the subsection Auto Run and launch options of:
    software-dl.ti.com/.../sdto_ccs_debug-handbook.html

    Another idea is to inspect the stack and heap usage by removing the modifier NOLOAD from the .lds file (there is a comment at the bottom of the file)

    I will try to think about additional scenarios and report back any findings.

    Hope this helps,
    Rafael
  • Correct code at MSMC allocation:

    Bad code at DDR0 allocation: 

    Crashed after 2 steps:

    Important note: when loading DDR0 variant a verification error occurs:

    Memory map settings:

    DDR Memory browser after GEL complete:

    DDR Memory browser after DDR3A_memory_test script:

    DDR Memory browser after load code:

    Why does the verification error occur? The memory map is installed correctly. The memory test is correct.

    I learned http://processors.wiki.ti.com/index.php/Troubleshooting_CCS_-_Data_Verification_Errors but did not find the answer.

  • Off NOLOAD is not affected.

    I tried to put in DDR0 different sections. The problem only occurs with the .text section in DDR0. Other sections are stored in DDR0 without errors.

  • In DDR0 variant I see error when load out file to DDR memory:

    OUT File:

    In MEMORY:

    Code offset UP to 0x2000 !

    Where can be the problem?

  • Hi,

    Please apologize for the delay; your replies went under the radar.

    I am not sure if you were able to find what is going on, but from the screenshots I can't help but think that some data signals on the external DDR memory are flaky, faulty or perhaps cross talk is conflicting some bits. I was trying to compare the successful and the faulty data to find a pattern to back this theory, but I was not able to do so.

    Unfortunately I don't have a better theory to explain what is going on, especially given that I am unable to reproduce this on the platforms I have here. Sorry.

    Regards,
    Rafael
  • Rafael,

    thank you very much for your answer!

    With DDR memory everything is fine, since I worked with Linux for six months on this board.

    Also, when I do so:

        .rsthand :
        {
            . = ALIGN(0x10000);
            KEEP(*(.isr_vector))
            *startup_ARMCA15.o (.text)
        } > DDR0
        
        . = ALIGN(4);
        .text :
        {
            *(.text*)
            *(.rodata*)
        } > MSMC_SRAM
    ......

    all works. Startup code allocate in DDR (startup_ARMCA15) at 0x80000000 and main code in SRAM at 0x0C000000. The code starts in DDR, then goes into SRAM and works correctly. 

    But when I allocate a .text section too in DDR, the CCS can not correctly load the code into memory and this problem (code shift) occurs. Disassembly of the out file give that the memory allocation is done correctly (fully similar to SRAM variant, difference only in addresses 0x0С000000 - 0x80000000). 

    My colleagues and I think that the most probable problem is the process of loading a out file into memory. Can I customize load options in CCS?

  • I think the problem is in the DDR memory configuration. I will look for. Thanks for answers.

  • Hi,

    Thanks for reporting back your suspicion. Linux does the DDR configuration via U-boot, thus it may be used as a baseline for your own configuration - the trick is finding where in the code the registers are actually written to the DDR peripheral (I am not familiar with u-boot code).

    Good luck in your investigation.

    Regards,
    Rafael