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New warning on ARM 16.3.0.STS

Michael Sch,
Intellectual 800 points


Hey guys,

with the TI ARM toolchain version 16.3.0.STS, the intrinsics for enabling/disabling interrupts have been optimized. This causes a new warning when compiling in Thumb mode:

"C:\Users\mike\AppData\Local\Temp\0970010", WARNING! at line 514: [W0004]
         Missing condition code inside of IT block
                CPSIE     i                     ; [DPU_4_PIPE0] |1538|

Please investigate and give feedback.

Regards,
Michael 

  • 0
    TI__Guru**** 251230 points

    This does appear to be a bug in the tools.  Please submit a test case to help us determine the cause and find a fix.  We need the preprocessed source file which causes this problem.  We also need to see the build options exactly as the compiler sees them.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Intellectual 800 points

    Here you are

    Fullscreen source.txt Download 
    ;* --------------------------------------------------------------------------*
||$C$L23||:    
        ADD       SP, SP, #28           ; [DPU_4_PIPE0] 
        POP       {V1, V2, V3, V4, V5, V6, PC} ; [DPU_4_PIPE1] 
        ; BRANCH OCCURS                  ; [] 
	.sect	".IO_DRIVER_CODE:IO_MPU_Enable"
	.align	16
	.clink
	.thumbfunc IO_MPU_Enable
	.thumb
	.asg	"no_stm_memcpy", memcpy
	.asg	"no_stm_memset", memset
	.global	IO_MPU_Enable

;*****************************************************************************
;* FUNCTION NAME: IO_MPU_Enable                                              *
;*                                                                           *
;*   Regs Modified     : A1,A2,A3,A4,V1,V2,V3,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi, *
;*                           D2,D2_hi,D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,*
;*                           D7_hi,FPEXC,FPSCR                               *
;*   Regs Used         : A1,A2,A3,A4,V1,V2,V3,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi, *
;*                           D2,D2_hi,D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,*
;*                           D7_hi,FPEXC,FPSCR                               *
;*   Local Frame Size  : 0 Args + 0 Auto + 16 Save = 16 byte                 *
;*****************************************************************************
IO_MPU_Enable:
;* --------------------------------------------------------------------------*
;** 504	-----------------------    if ( region_id < 4u ) goto g3;
;** 554	-----------------------    return 31;
        CMP       A1, #4                ; [DPU_4_PIPE0] |504| 
        STR       LR, [SP, #-4]!        ; []  PUSH {V1, V2, V3, LR} ; [DPU_4_PIPE0] 
        STR       V3, [SP, #-4]!        ; []  PUSH {V1, V2, V3, LR} ; [DPU_4_PIPE0] 
        STR       V2, [SP, #-4]!        ; []  PUSH {V1, V2, V3, LR} ; [DPU_4_PIPE0] 
        STR       V1, [SP, #-4]!        ; []  PUSH {V1, V2, V3, LR} ; [DPU_4_PIPE0] 
        IT        CS                    ; [] 
        MOVCS     A1, #31               ; [DPU_4_PIPE0] |554| 
        MOVW      A2, IO_MPU_regionInitialized+0 ; [DPU_4_PIPE0] |507| 
        BCS       ||$C$L24||            ; [DPU_4_PIPE1] |554| 
        ; BRANCHCC OCCURS {||$C$L24||}   ; [] |554| 
;* --------------------------------------------------------------------------*
;**	-----------------------g3:
;** 507	-----------------------    if ( IO_MPU_regionInitialized[region_id] ) goto g5;
;** 554	-----------------------    return 33;
        MOVT      A2, IO_MPU_regionInitialized+0 ; [DPU_4_PIPE0] |507| 
        LDRB      A2, [A2, +A1]         ; [DPU_4_PIPE0] |507| 
        CMP       A2, #0                ; [DPU_4_PIPE0] |507| 
        IT        EQ                    ; [] 
        MOVEQ     A1, #33               ; [DPU_4_PIPE0] |554| 
        MOVW      A3, IO_MPU_regionEnabled+0 ; [DPU_4_PIPE0] |511| 
        BEQ       ||$C$L24||            ; [DPU_4_PIPE1] |554| 
        ; BRANCHCC OCCURS {||$C$L24||}   ; [] |554| 
;* --------------------------------------------------------------------------*
;**	-----------------------g5:
;** 511	-----------------------    K$15 = &IO_MPU_regionEnabled[region_id];
;** 511	-----------------------    if ( !*K$15 ) goto g7;
;** 554	-----------------------    return 330;
        MOVT      A3, IO_MPU_regionEnabled+0 ; [DPU_4_PIPE0] |511| 
        ADDS      A3, A3, A1            ; [DPU_4_PIPE0] |511| 
        LDRB      A2, [A3, #0]          ; [DPU_4_PIPE0] |511| 
        CMP       A2, #0                ; [DPU_4_PIPE0] |511| 
        IT        NE                    ; [] 
        MOVNE     A1, #330              ; [DPU_4_PIPE0] |554| 
        BNE       ||$C$L24||            ; [DPU_4_PIPE1] |554| 
        ; BRANCHCC OCCURS {||$C$L24||}   ; [] |554| 
;* --------------------------------------------------------------------------*
;**	-----------------------g7:
;** 523	-----------------------    saved_cpsr = _disable_IRQ();
;** 526	-----------------------    saved_fiqs = *(C$1 = (volatile unsigned *)0xfffffe30u)&0xc00u;
;** 527	-----------------------    C$1[4] = 3072u;
;** 532	-----------------------    *K$15 = 1;
;** 535	-----------------------    _mpuSetRegion_(region_id+8u);
;** 535	-----------------------    mpu_status = _mpuGetRegionSizeAndEnable_();
;** 535	-----------------------    _mpuSetRegionSizeAndEnable_(mpu_status |= 1u);
;** 538	-----------------------    *C$1 = saved_fiqs;
;** 541	-----------------------    if ( saved_cpsr&0x80u ) goto g9;
        MRS       V2, CPSR              ; [DPU_4_PIPE0] |523| 
        CPSID     i                     ; [DPU_4_PIPE0] |523| 
        MOVW      V3, #65072            ; [DPU_4_PIPE0] |526| 
        MOVT      V3, #65535            ; [DPU_4_PIPE0] |526| 
        MOVS      A2, #1                ; [DPU_4_PIPE0] |532| 
        STRB      A2, [A3, #0]          ; [DPU_4_PIPE0] |532| 
        ADDS      A1, A1, #8            ; [DPU_4_PIPE1] |535| 
        LDR       V1, [V3, #0]          ; [DPU_4_PIPE0] |526| 
        MOV       A2, #3072             ; [DPU_4_PIPE1] |527| 
        STR       A2, [V3, #16]         ; [DPU_4_PIPE0] |527| 
        BL        _mpuSetRegion_        ; [DPU_4_PIPE1] |535| 
        ; CALL OCCURS {_mpuSetRegion_ }  ; [] |535| 
;* --------------------------------------------------------------------------*
;** 543	-----------------------    _enable_IRQ();
;**	-----------------------g9:
;** 554	-----------------------    return 0;
        BL        _mpuGetRegionSizeAndEnable_ ; [DPU_4_PIPE1] |535| 
        ; CALL OCCURS {_mpuGetRegionSizeAndEnable_ }  ; [] |535| 
        ORR       A1, A1, #1            ; [DPU_4_PIPE0] |535| 
        BL        _mpuSetRegionSizeAndEnable_ ; [DPU_4_PIPE1] |535| 
        ; CALL OCCURS {_mpuSetRegionSizeAndEnable_ }  ; [] |535| 
        AND       V1, V1, #3072         ; [DPU_4_PIPE0] |526| 
        STR       V1, [V3, #0]          ; [DPU_4_PIPE0] |538| 
        LSRS      A1, V2, #8            ; [DPU_4_PIPE1] |541| 
        IT        CC                    ; [] 
        CPSIE     i                     ; [DPU_4_PIPE0] |543| 
        MOVS      A1, #0                ; [DPU_4_PIPE0] |554| 
;* --------------------------------------------------------------------------*

    C_OPTS      :=  -mv7R4                         \
                --abi=eabi                     \
                --auto_inline=0                \
                --endian=big                   \
                --float_support=VFPv3D16       \
                --plain_char=unsigned          \
                --small_enum                   \
                --fp_mode=strict               \
                --opt_level=2                  \
                --opt_for_speed=3              \
                --code_state=16                \
                --no_inlining                  \
                --gen_func_subsections         \
                --check_misra=none             \
                --issue_remarks                \
                --display_error_number         \
                --quiet                        \
                --aliased_variables            \
                --no_stm                       \
                --unaligned_access=off

  • 0 in reply to Michael Sch,
    TI__Guru**** 251230 points

    Thank you for showing the build options.  The file you attached is not the one needed.  It shows the assembly output of the compiler.  I need the C source which the compiler processes to generate the problem assembly.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Intellectual 800 points

    George,

    I see. Unfortunately I cannot post the output of this pp file here as it would unveil huge pieces of our production code.

    So I came up with an alternative. This minimal code piece is perfectly suitable to reproduce the problem:

    void testfunction (void)
{
    unsigned int saved_cpsr;

    /* save and disable IRQs locally */
    saved_cpsr = (unsigned int)_disable_IRQ();
  
    /* do some critical section handling here */
    
    /* restore IRQs */
    if ((saved_cpsr & 0x00000080UL) == 0U)
    {
        (void)_enable_IRQ();
    }
}

    Regards,
    Michael

  • 0 in reply to Michael Sch,
    TI__Guru**** 251230 points

    Thank you for the test case.  I can reproduce the problem.  I filed SDSCM00052849 in the SDOWP system to have this investigated.  You are welcome to follow it with the SDOWP link below in my signature.

    Thanks and regards,

    -George