I am trying to avoid a frame buffer and use a USB3 to RGB conversion IC (Cypress FX3) for direct input to the RGB pins of the DLPC900. The FX3 IC would generate the PCLK, HSYNC, VSYNC etc.
The on-board buffering of that FX3 IC could buffer only one or two rows of DMD pixels data.
If I can guarantee the PCLK/HSYNC/VSYNC timings for at least one row of pixels will the DLPC900 work correctly?
Another way to think of it: if I were to add a variable delay to HSYNC after one row has completed and before starting the next row, WHILE keeping the PCLK continuous, will that cause issues with the DLPC900?
Subsequent question: what if I can only buffer a subset of a single row in which case I would effectively have to clock-stretch while transmitting data to the DLPC900, would the DLPC900 be OK with this?
Thanks.