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DLPC410: THE INIT_ACTIVE is always high

Part Number: DLPC410
Other Parts Discussed in Thread: DLPLCR65NEVM,

HI,

My setup:DLPC410  VIRTEX-5  DLPLCR65NEVM

First, DMD can correctly load display data when using GUI. But when I programmed with Verilog myself, I encountered some problems.

1、The INIT_ACTIVE is always high, About ARST (pll_ locked_ rstz_ gq) I refer to the VHDL reference code, and the training mode can also be captured on the chipscope as temp_ dout_ a.

2、I use ISE's chipscope to grab ddc_ version and DMD_ Type, ddc_ version [2:0] is 3 'B111, dmd_ type is 4'b1111. This indicates that the DMD is not connected correctly, but I can load the picture display through the GUI.

3、If the GUI is used to load pictures, D9 and D10 (LED0 and LED1) will be on. However, whenever I burn a program and grab a signal with chipscope, only D2 on the board will be on and the other LEDs will be off. Is this normal.

I'm sure my problem is that the initialization process has not been successfully completed. Unfortunately, I haven't been able to solve the problem. I hope I can find the answer here.

Thanks.

  • Hello Tian,

    You must send training patterns as described in the DLPC410 data sheet for initialization to complete successfully.  Note that the heartbeat may not run if initialization is not completed.

    At the beginning the APPS_FPGA must pull the DLPC410 into logic reset and begin running the  training patterns on all 2xLVDS lines into the DLPC410 (i.e. Data, SCTRL, & D_VALID lines).  Once the patterns are running (give some clock cycles to make sure they are stable) and then release the DLPC410 from logic reset and then wait for Init_Active to go low.

    Fizix

      

  • Hello Fizix,

    As for the training patterns, my understanding is that after all LVDS data are calibrated correctly and kept stable for a period of time, pull up the ARST and wait for init_ Active to go low. therefore

    At the beginning the APPS_FPGA must pull the DLPC410 into logic reset and begin running the  training patterns on all 2xLVDS lines into the DLPC410 (i.e. Data, SCTRL, & D_VALID lines).

    1. How many clock cycles are required to ensure that they are stable.

    2. The Sys CLK and IO CLK I set are 200M clock and 400M clock. Are they correct.

    3. How long does the ARST need to be kept high? The reference code is 70ns.

    Tian

  • Tian,

    According to the DLPC410 data sheet the 1/2 speed "system clock" is derived (internally generated) and is not a direct input.  If you are putting 200 M into some other pin, this may be the issue.  There is s reference clock that should be fed from the 50 MHz oscillator or a passthrough from it. The signal name is CLKIN_R

    Fizix

  • Hi, Fizix

    I found my problem. My understanding of the reference code is wrong. The ARST signal does not only remain 70ns, but remains high after the declaration. Now I can normally monitor INIT_ ACTIVE signal, and the LED flashes normally.

    Thank you very much for your help.

    Tian

  • Tian,

    This is fantastic news!  I am glad you figured it out.

    Fizix