Other Parts Discussed in Thread: DLP9500, DLPLCRC410EVM,
Hello,
According to the datasheet of DLP9500,the max pattern rate is 23418Hz. But DLPLCRC410EVM can not meet the requirment.
So, how can I design to meet the requirment as much as possible? Change FPGA, change to DDR3 or some others?
Thanks!