Other Parts Discussed in Thread: DLP9000X
Hello.
My question is about the layout guidelines of the DLPC910.
- My design is DLPC910 and DLP9000X.
- in the DLP9000X, for each pin in the datasheet of the Differential buses (A, B, C, D) there is data of the internal length (in mils) to consider in layout.
- that said, I was under the impression that this information will also be given to the DLPC910 In & Out differential buses as those are actually Xilinx FPGAs
am i missing something? how do i take into account the internal lengths of the DLPC910
BR
ML
