This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLPC910: DLPC910 layout guidelines clarifications

Part Number: DLPC910
Other Parts Discussed in Thread: DLP9000X, DLP9000

Hi.

We are in the layout phase of the DLPC910, and a few issues are not clear. Will Appreciate your abbreviation on the matter below: 

1. In section "10.1.3.2.1 LVDS Output Bus Skew", it is written that:

"To minimize instantaneous AC current switching in the DMD, the LVDS output bus trace lengths should differ to
produce a recommended 100-200 ps skew from one bus to another. Table 10-4shows two examples how buses
can be skewed assuming 180-200 ps per 1000 mils. Keep in mind the total skew from one bus to another should
be kept below the maximum skew for the DMD.



In Table 10-4 two examples are given for LVDS OUT. (See attached). in one example there is delta of ~2200mil between Group A-B, and ~1700mil between group B-C, and 1050mil between group C-D... but 
on Example 2....Group A-B has no delta and C-D also are same length...which contradict the text highlighted in orange above.

      - our questions are:
            - does this delta is mandatory between each group to another? If yes, what is the min and max to keep? and why example 2 doesn't include that? the current instructions impose long tracng to keep 
               those deltas which are very difficult for our case where the DLPC910 is very close to the FLEX connector

                - is it only for LVDS OUT? What about LVDS IN groups?
                          - what are the requirements for LVDS IN Groups? Is there a requirement to keep skew between each group to other? A to B, B to C, C to D? 
              


 

  • Hi Moshe, Fizix and I discussed these questions yesterday and will need more time to respond. 

    Also, did the IBIS file help with your other question?

    Regards,

    Matt

  • Thank you very much for the prompt reply Matt. looking to hear from you ASAP as we are stuck with layout

  • Hi Moshe,

    This information in the datasheet is creating unnecessary confusion. We have logged a ticket to fix this.

    While the information in the paragraph is accurate – skewing the LVDS trace lengths from one another will help to minimize instantaneous AC current switching in the DMD and potentially help to minimize EMI, the information contained in Table 10-4 needs to be updated.

    We will remove 10.1.3.2.1 from the datasheet altogether to prevent any confusion in what is required for layout/skew matching on the LVDS interface.

    To answer your questions:

                - does this delta is mandatory between each group to another? If yes, what is the min and max to keep? and why example 2 doesn't include that? the current instructions impose long tracng to keep

                   those deltas which are very difficult for our case where the DLPC910 is very close to the FLEX connector

                  TI Answer: No, this delta is not mandatory, the information provided in section 10.1.3.2.1 is optional.

     

                  - is it only for LVDS OUT? What about LVDS IN groups?

                  TI Answer: Again, this delta is not mandatory, and the information provided in section 10.1.3.2.1 should be considered optional.

     

                   - what are the requirements for LVDS IN Groups? Is there a requirement to keep skew between each group to other? A to B, B to C, C to D?

                  TI Answer: Again, this delta is not mandatory, and the information provided in section 10.1.3.2.1 should be considered optional.

     

    The requirements for the LVDS IN Groups are described in Table 10-3:

    The DATA IN differential signals ( DDC_DIN[A,B,C,D][0:15]_DP[N,P] ) and DVALID_[A,B,C,D]_DP[N,P] associated with that bus should all be matched to within 50 mils of the CLK IN differential signal ( DDC_DCLK_[A,B,C,D]_DP[N,P] ) associated with that bus.

    Thanks again for finding this item that needs to be updated.

    Regards,

    Matt

  • Thank you very much Matt.

    now it makes sense. :-)

    one more question...

    do i need to route the groups as seperate bundels or can route them as one big group (keeping the tolerance of each group to its cloxk as you mentioned) . the question is for both the in and out lvds groups

  • Matt. to be more clear. those are my questions:

    The guidelines for the LVDS out. are?
    - I need to route each Group A/B/C/D as a bundle

    - each group should be routed within 50 mil of its clock (taken from datasheet table 10-3)

    - how much skew do i need to keep from one group to another (i.e: from group A to B, B to C, C to D, A to D, etc)? and does this skew need to be accounted to the overall path to the DLP9000X?

  • Hello Moshe,

    I need to verify with our layout folks, but I don't see any reason that it cannot be one bundle for all as long as each data pair are within the 50 mil of it's respective clock as you point out.

    As far as the skew between buses.  The DLP9000/DLPC9000X DMD datasheet [DLPS036B starting on pg. 16] spells this out in section 7.7 Timing Requirements.  For each side of the DMD (A and B) and (C and D), the skew is listed as +/- 1.04 ns.  Between the sides (AB to CD) is more forgiving.  For the DLP9000X +/- 2 ns should be OK for the AB to CD skew.

    The skew does need to be accounted for from the FPGA to the DMD including internal trace lengths in the DMD as listed in the Pins Function table of the DLP9000/DLPC9000X DMD datasheet starting on page 5.

    Fizix

  • Hi Fizix.

    Thank you. noted!