DLP500YX: DLP500YX detailed port documentation

Danilo A.

Part Number: DLP500YX
Other Parts Discussed in Thread: DLPC900

Hi Team,

We received this inquiry from our customer.

I'm designing a volumetric display where DLP500YX DMD would be a great fit due to it's fast frame rate capability. However I would like to drive it directly from an FPGA in order to be able to stream 1 bit video at 16kHz frame rate, but I could not find documentation about the protocol used on the LVDS data input ports, as well as detailed description of some other ports. Is this information available (perhaps with some terms/conditions, or an NDA requirement)?

As far as I can tell, the DLPC900 controller can only achieve the maximum 1 bit pattern rate of 16kHz when having them pre-stored on the embedded DRAM because the video input ports have limited bandwidth..

I understand that by not using the DLPC900 controller there is a risk of damaging the DMD or shortening it's lifespan, but I am ok with that risk.

Regards,

Danilo

over 2 years ago

0 Matt Soucek over 2 years ago

TI__Expert 3700 points

Hi Danilo,

There are a large number of design house resources that a customer can contact for designs that are not using the standard TI chipsets. Here is the link on ti.com: https://www.ti.com/design-resources/embedded-development/dlp-chip/display-and-projection.html

Regards,

Matt

0 Danilo A. over 2 years ago in reply to Matt Soucek

TI__Mastermind 25955 points

Hi Matt,

Thank you for your response. Here is the feedback of our customer.

Thank you for looking into my request and for providing the link, but actually I'm not looking to use a chipset from another vendor but rather to develop my own, so what I meant is that I'm looking for more technical documentation on the DMD chip ports than what is available in the datasheet i.e. what is the mapping between the DMD SRAM address space and the mirrors, how do I control which SRAM address to write to, and how do I instruct the DMD to move the mirrors to the position defined in the SRAM, so things like timing diagrams, address mappings, etc.. Is that available? I could not find it in the datasheet or the associated documentation for the DLP500YX...

Regards,

Danilo

+1 Matt Soucek over 2 years ago in reply to Danilo A.

TI__Expert 3700 points

Hi Danilo,

This is TI proprietary information. Even with an NDA, we do not provide the level of information that the customer is requesting.

Regards,

Matt

0 Danilo A. over 2 years ago in reply to Matt Soucek

TI__Mastermind 25955 points

Hi Matt,

Our customer has a follow up inquiry below.

I see.. can I ask what kind of information is available under NDA? Of course I'm not seeking any information about the chip's internals, I just need to know how to interface it (how to set a given mirror to an on or off position) without using one of your controller chips.

Regards,

Danilo

+1 Carey Ritchey over 2 years ago in reply to Danilo A.

TI__Intellectual 1865 points

Danilo

All TI DLP DMDs must be used with a TI DLP controller for correct and safe operation per the TI datasheet.

Please feel free to share my email contact with the customer if they require more details

at carey.ritchey@ti.com

Regard

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DLP500YX: DLP500YX detailed port documentation