Other Parts Discussed in Thread: DLPC3430
According to document DLPS057E, I2C port 0 (the slave port) is Type 7 (referenced to VCC_INTF) and I2C port 1 (the bus master port) is Type 8 (referenced to VCC18). The reference design shows the master controller's I2C port0 (his bus slave port) connected to a host processor, and I2C port1 (his bus master port) connected to the slave controller's port0 (his bus slave port) presumably for inter-chip communication, with the slave controller's port1 (his 1.8V referenced bus master port) unused.
With the two controllers set to use a VCC_INTF voltage of 3.3V to interface with a 3.3V host CPU, this implies that the master controller's I2C port0 will properly be a 3.3V I2C to serve as a peripheral to a host CPU, but the master controller's 1.8V referenced I2C port1 will be tied to the slave controller's 3.3V referenced I2C port0.
Is this a problem?
Since these devices have a 3.3V interface option, and must be used in pairs, presumably TI has run this configuration.
Is the Master port 3.3V tolerant even though referenced to 1.8V?
Is an I2C level shift needed between the two DLPC3439 controllers, and if so, is there a solution TI uses and/or recommends?
On a related note, I see that the parallel input port pins are Type10, which Table 5-10 labels "Reserved", specifies no reference voltage, and the voltage tables neglect any mention of Type10 signals for things like thresholds. This seems odd, since the docs indicate that the parallel interface is referenced to VCC_INTF. Is there an update to this? Should we assume the limits and thresholds on the parallel port are fairly generic 3.3V related values?