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DLP660TE: How to display DMD native resolution of 2716x1528 correctly

Part Number: DLP660TE
Other Parts Discussed in Thread: DLPC4422, DLPDLCR660TEVM, DLPLCRDC4422EVM

Hello, TI team!
How can I correctly display DMD native resolution of 2716x1528?
I asked China's team, and they answered yes.
1. only two resolutions are supported for Vby1 input signal.
2. If it is a 3840x2160 input signal, set XPR ON UHD.
3. If it is a 2712x1528 input signal, set XPR OFF 2WAY.
Then, according to the requirements of DLP660te _ VX1 _ Input _ Video _ Timings, I input 2712x1528 signal to FPGA after booting, and then set XPR OFF 2WAY, but at this time, the DMD screen will flash or show nothing, and then enter SOLIDFIELD mode.

What I want to ask is,
1. Are my operation steps correct?

2. We have found two front-end board suppliers, whose input resolution is 3840x2160, and setting XPR ON UHD can display normally. However, if the signal is input at 2712x1528 and XPR OFF 2WAY is set, it can't be displayed correctly. Different Video_Timings parameters have been tested and modified, but it still can't be displayed correctly. Any good suggestions?

3. Why does DLP enter SOLIDFIELD mode?

4. I checked the serial port printing information. In XPR ON UHD mode, the following data is displayed:
Event: Source Stable Detected on channel
ALC: 15 4705 SD_STABLE
datapathf: Transition to ATTEMPCOMPLETE
In XPR OFF UHD mode, the following data is displayed:
Event: Source Stable Detected on channel
ALC: 21 4691 SD_STABLE
Could you please explain this mistake?

5. We also have access to related similar problems, such as But this can't solve my problem, because the post only stated that they solved the 4K display by adjusting the frequency, and then said that the can project 2.7K pattern successfully and turn off XPR manually in FPGA control page, but did not explain how to solve the 2.7 resolution display.

I am very grateful to TI team for helping me solve this problem.

  • Hello Junfa Ye,

    To confirm, you have the reference input timing table?

    The process you have stated is correct but it seems that the input timing is off. Unfortunately, the FPGA in the DLPC442x design does not auto-lock.

    The XPR feature should be changed on the 'FPGA Control' page. You may also utilize the 'Autolock' page to show the status of the timing.

    Hopefully this helps!



  • Thank you for your reply!
    I have reference input timing table.
    Why input timing is off?

    We'd like to see the DEMO. Could you please help us test the 2712x1528 input signal?
    Thank you very much!

  • Hello Junfa Ye,

    A demonstration with 2712x1528 input would look the same as a functional 3840x2160 input. I don't think that will be helpful in this case. If you are confused in how the system would look set up, please see the EVM User's Guide here.

    We hope you can help us understand more about your setup and the issue at hand, here are a few things we need:

    • References to which front-ends you are utilizing and considering, we aren't sure if these front-end chips can handle this unconventional resolution, although UHD could be supported
    • Images of your steps you are taking while configuring changes on the GUI as well as what timing is being utilized when this is being done
    • Software version you are utilizing



  • OK, thank you. Here is the reply.

    • The chip supports downward compatibility with 2712*1528 resolution.
    • We use HDMI signal to transmit computer images. All the 2712*1528 timing has been tested. 
    • FPGA uses XPR_FPGA_2WAY_UHD_A5_v356.
    • DLP uses 
  • Hey Junfa Ye,

    Please advise the chips you're using as a front-end, for the time being I'll test this the same way we tested previously.

    Unfortunately this means I can't recreate it as accurately.



  • OK, our chip models are MST6190 and MST9U13Q1.
    Looking forward to your good news, thanks!

  • Hello Junfa Ye,

    Do you have a link to the solution you ordered or are you building with these chips? You typically need to work with the front-end manufacturers to make sure the settings you're trying to implement can be sent through their chips.

    After following the test procedures explained previously I was able to get an image on our DMD. I utilized line #8 of the recommend video timings - 2712x1528@60. 

    I would highly recommend you (1) read through the 'Software Programmers Guide' to flash program the ASICs and afterward (2) follow the 'UHD FPGA Programming guide' to flash the FPGA. It shouldn't be the case from out-of-box use but the FPGA might be different and reprogramming the FPGA would fix the FPGA to the 0.66 DMD instead of the 0.47 DMD.

    Please note if can display input at 3840x2160, you only need to change the input and set 'XPR OFF 2WAY' on the 'FPGA Control' tab on the DLPC4422 GUI.

    Hopefully this helps!



  • Hi Aaron,
    I'm glad to see that there is an image at 2712x1528. I've read' Software Programmers Guide' and' UHD FPGA Programming guide' and confirmed that there is a correct program. I think maybe the 4422 or front-end board is not configured well.

    We are working with front-end manufacturers, who are debugging the software. At present, there is no communication between 4422 and front-end board, and the source switching operation is based on GUI.

    I still want to know the operation steps of 4422,
    My current steps are as follows: After powering on and booting, I see that the 4422 will enter the splash mode, and after a while the splash picture disappears, the 4422 will enter the external XPR ON UHD mode, and then start detecting the source signal. At this time, if:
    1. Input 3840x2160 vb1 signal, and the image will be displayed;
    2. Input 2712x15280 vb1 signal, the picture flashes and then enters the SOLIDFIELD, and then set' XPR OFF 2WAY', the picture flashes for a while or no image is displayed directly.
    3. If vb1 signal is not input, it will also enter SOLIDFIELD.

    Can you explain your operation steps in detail?

    In addition, is it possible that it is a source detection problem? The following is the description of Source Detection. At present, I only enable AUTOLOCK Config. If I disabled both of them, what do I need to update the Source Configuration through I2C?

  • Hello Junfa Ye,

    When the FPGA is not receiving a valid timing - very sensitive - the projection mode (see 'Display' tab) will default to 'SOLIDFIELD'. If you are worried about the 4422 configuration - feel free to reflash the ASICs or FPGA, as shown above in my test, I utilized what is currently available on

    The producer of your front-end chips should be able to provide a working configuration of the timings we've provided and you've mentioned you have. They might possibly have a test module.

    Are you working with the EVMs we offer - DLPLCRDC4422EVM and DLPDLCR660TEVM?

    To get a working 2712x1528 I performed the below steps on the 2 mentioned EVMs we provide on

    1. Install DLPC4422 GUI
    2. Download DLP660TE Firmware
    3. Attach cables; USB, power and DMD Flexcables
    4. Reset Bus on GUI 'Flash Loader' until recognized with an address
    5. Program the ASIC flash following the 'Software' Programmers Guide'
    6. Program the FPGA following the 'UHD FPGA Programming guide'
    7. Power on the DMD with the SW1 - Splash screen should follow
    8. Turn off DMD and input UHD timing
    9. Turn on DMD - Test pattern generator input is displayed, 'Display' tab utilizes 'EXTERNAL' Projection Mode
    10. Autolock timing updates after performing a 'Get', reflecting closely what I'm expecting as an input
    11. Turn off DMD and change input to 2712x1528 as well as SET 'XPR OFF 2WAY' - just click 'Set'
    12. Turn on DMD - Test pattern generator input is displayed, 'Display' tab utilizes 'EXTERNAL' Projection Mode
    13. Autolock timing updates after performing a 'Get', reflecting closely what I'm expecting as an input

    The most likely issue is your input is incorrect in this case as 2712x1528 is not a typical setting of input. Please note that autolock doesn't need to be set.



  • Hi Aaron,

    I will test according to your steps. Excuse me, how can I turn off and turn on DMD?


  • Hello Junfa Ye,

    Please see #7 - "Power on the DMD with the SW1" (Switch #1). This is also referenced on the EVM User's Guide.

    Good luck!



  • Hi Aaron,
    I have used DMD on/off, but I found that this operation seems to have no effect on switching modes.
    I disenable 'autolock config' and updated flash, and found that it was impossible to switch to external mode. So I have to restore flash usage.
    I think this non-display may be caused by the input signal, and I will continue debugging.
    Finally, thank you very much for your support!