DLP660TE: How to display DMD native resolution of 2716x1528 correctly

Hello Junfa Ye,

To confirm, you have the reference input timing table?

The process you have stated is correct but it seems that the input timing is off. Unfortunately, the FPGA in the DLPC442x design does not auto-lock.

The XPR feature should be changed on the 'FPGA Control' page. You may also utilize the 'Autolock' page to show the status of the timing.

Hopefully this helps!

Best,

Aaron

Thank you for your reply!
I have reference input timing table.
Why input timing is off?

We'd like to see the DEMO. Could you please help us test the 2712x1528 input signal?
Thank you very much!

Hello Junfa Ye,

A demonstration with 2712x1528 input would look the same as a functional 3840x2160 input. I don't think that will be helpful in this case. If you are confused in how the system would look set up, please see the EVM User's Guide here.

We hope you can help us understand more about your setup and the issue at hand, here are a few things we need:

• References to which front-ends you are utilizing and considering, we aren't sure if these front-end chips can handle this unconventional resolution, although UHD could be supported
• Images of your steps you are taking while configuring changes on the GUI as well as what timing is being utilized when this is being done
• Software version you are utilizing

Best,

Aaron

OK, thank you. Here is the reply.

• The chip supports downward compatibility with 2712*1528 resolution.
• We use HDMI signal to transmit computer images. All the 2712*1528 timing has been tested. 
• FPGA uses XPR_FPGA_2WAY_UHD_A5_v356.
• DLP uses 

Hey Junfa Ye,

Please advise the chips you're using as a front-end, for the time being I'll test this the same way we tested previously.

Unfortunately this means I can't recreate it as accurately.

Best,

Aaron

OK, our chip models are MST6190 and MST9U13Q1.
Looking forward to your good news, thanks!

Hello Junfa Ye,

Do you have a link to the solution you ordered or are you building with these chips? You typically need to work with the front-end manufacturers to make sure the settings you're trying to implement can be sent through their chips.

After following the test procedures explained previously I was able to get an image on our DMD. I utilized line #8 of the recommend video timings - 2712x1528@60. 

I would highly recommend you (1) read through the 'Software Programmers Guide' to flash program the ASICs and afterward (2) follow the 'UHD FPGA Programming guide' to flash the FPGA. It shouldn't be the case from out-of-box use but the FPGA might be different and reprogramming the FPGA would fix the FPGA to the 0.66 DMD instead of the 0.47 DMD.

Please note if can display input at 3840x2160, you only need to change the input and set 'XPR OFF 2WAY' on the 'FPGA Control' tab on the DLPC4422 GUI.

Hopefully this helps!

Best,

Aaron

Hi Aaron,
I'm glad to see that there is an image at 2712x1528. I've read' Software Programmers Guide' and' UHD FPGA Programming guide' and confirmed that there is a correct program. I think maybe the 4422 or front-end board is not configured well.

We are working with front-end manufacturers, who are debugging the software. At present, there is no communication between 4422 and front-end board, and the source switching operation is based on GUI.

I still want to know the operation steps of 4422,
My current steps are as follows: After powering on and booting, I see that the 4422 will enter the splash mode, and after a while the splash picture disappears, the 4422 will enter the external XPR ON UHD mode, and then start detecting the source signal. At this time, if:
1. Input 3840x2160 vb1 signal, and the image will be displayed;
2. Input 2712x15280 vb1 signal, the picture flashes and then enters the SOLIDFIELD, and then set' XPR OFF 2WAY', the picture flashes for a while or no image is displayed directly.
3. If vb1 signal is not input, it will also enter SOLIDFIELD.

Can you explain your operation steps in detail?

In addition, is it possible that it is a source detection problem? The following is the description of Source Detection. At present, I only enable AUTOLOCK Config. If I disabled both of them, what do I need to update the Source Configuration through I2C?

Hi Aaron,

I will test according to your steps. Excuse me, how can I turn off and turn on DMD?

Thanks!