Dear
I want the HOST_IRQ pin to change every time a video playback ends.
I tried following the steps in section "4.4 Host IRQ Interrupt Signal" and "4.1.6 Example 5: Display 3+ Videos/Images Seamlessly" in the "FPGA User's Guide".
But it didn't work, as long as any Interrupt Enable is set, HOST_IRQ always stays high and I don't know how to set FPGA Interrupt Set or Clear.
Regarding the following steps, do you think my understanding is incorrect?
- MCU sends the read FPGA Interrupt SET instruction via MOSI:{0x01 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00}
- MCU receives the FPGA Interrupt SET data sent back by FPGA via MISO:{0x00 0x01 0x04 0x00 0x00 0x00 0x00 0x00 0x05}
- MCU sends the clear FPGA Interrupt CLR instruction via MOSI:{0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x01}
- At this point, HOST_IRQ will be pulled low until the condition set by Interrupt Enable (0x08) is met, then HOST_IRQ will return to high.
Assuming that the VID_LOP_COMP_IRQ of the FPGA Interrupt Enable (0x08) is High, and then repeating the actions 1~3, then HOST_IRQ will be pulled back to High each time a video is finished playing.
Do you have any other operation suggestions in addition to the following MSP430 sample program?
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Thank you for reading and your assistance.