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DLPR910: DLPR910 flash replacement design

Part Number: DLPR910

Hello. 

I have few questions in regard to latest announcement that the DLPR910 will be obsolete soon

- Instructions to move the Master SPI mode with flash given in the following link: https://www.ti.com/lit/er/dlpt030/dlpt030.pdf?ts=1689870545882

- In the above link document, it is mentioned to base the design of DLPLCRC910EVM.

- Looking at the document some uncertainties rise. Looking at DLPLCRC910EVM.  I have some questions in regards to connectivity:

            - FLASH CSn

              - Is controlled from DLPC910 pin AA10 which is DLPC_I2CADDR_SEL....how is that possible? I have also in my design two DLPC910...so in order to enable the CSn they will have same address?!?

              - the CSn also as option to route to pin N18 (CS_B_0in the EVM schematics - not populated)...but per DLPC910 datasheet, this pin is defined as GND.....?!?!

                 - for what purpose this option?

                - Which is correct? CS_B_0 or GND?

                - who should control the CSn?

         - FLASH  DIN

               - In the EVM Schematics, this pin is controlled by Micro Controller GPIO which is routed also to the DLPC910 pin AA9 which is reserved. can you explain?

         - How should I program the flash?
            - in the EVM there is option through GPIO or connector 
            - In the Errata it is stated that "End customer will program the SPI flash, either before PCB assembly or via the Xilinx tools after assembly"
               - Does it mean by Vivado? IF I have an FPGA and a flash (no TI related) to have the SPI shared just use different CSn?

               - Do you recommend/use any tool to program it from the connecotor?
               

  • Hello Moshe,

    My first recommendation if you have not done so already, is to download the schematic for the new DLPLCRC910EVM board found here:  https://www.ti.com/lit/zip/dlpr108 

    On page 10 of the schematic it shows a box in the lower left corner with configuration changes for the SPI PROM.

    The header that is on the EVM board will work with a Cheetah SPI programmer.  I believe CSn will be controlled by your programming device.

    I suspect that you will have to use a separate SPI for each DLPC910

    The N18 pin on the newer schematic shows a 1K pulldown to ground instead of a hard ground.

    Some of the pins are multi-functional.  They behave one way when configuring the DLPC910 and another once configuration is complete.

    These are preliminary answers until I can get more detailed answers.

    Fizix

  • Hello Moshe,

    I am looking to get more detail on this today or tomorrow.  We know that you need to get started on layout.

    Fizix

  • Hi Fizix,
    Noted. waiting for your input

  • Moshe,

    I am still waiting on a few pieces of information. Thank you for your patience on this.

    Fizix

  • Hello again Moshe,

    USEFUL DOCUMENTS:
    DLP LightCrafter DLPC910 Evaluation Module User's Guide

    DLPLCRC910EVM Design Files 

     

    Instructions to move the Master SPI mode with flash given in the following link: https://www.ti.com/lit/er/dlpt030/dlpt030.pdf?ts=1689870545882.

     

    In the above link document, it is mentioned to base the design of DLPLCRC910EVM.

    Looking at the document some uncertainties rise. Looking at DLPLCRC910EVM.  I have some questions in regards to connectivity:

    FLASH CSn

    Is controlled from DLPC910 pin AA10 which is DLPC_I2CADDR_SEL....how is that possible?

    During configuration from the SPI Flash, this pin is an output from the FPGA to control CSn.  The FPGA pulls it low, but if J10 is populated it is already low so no conflict.

    However, when the FPGA configures it become an input which it uses to read the state of J10 to determine the I2C address for the DLPC910.

     I have also in my design two DLPC910...so in order to enable the CSn they will have same address?!?

    You will have to follow the Xilinx documentation on using SPI Flash with the FPGA.  I suspect that you will end up having to use two separate SPI Flash chips because it has shared functionality on the CS pin.  Since the SPI Flash is small and relatively inexpensive and the configuration file will be freely available for download soon, it may simply be easier for you to use one SPI Flash for each FPGA.  We do not provide support to use only one SPI Flash.

     The CSn also as option to route to pin N18 (CS_B_0in the EVM schematics - not populated)...but per DLPC910 datasheet, this pin is defined as GND.....?!?!

    For what purpose this option?

    This is currently reserved and not used at this time.

     

    Which is correct? CS_B_0 or GND?  

    This question does not make sense.  Previously it was grounded, but it was still connected to pin N18 which is CS_B_0 on the DLPC910.  It is now connected via R112 (a 1K Ohm resistor) to ground.

    Also associated with it is:

    • R695 (a DNI 4.7K Ohm resistor to 3.3 V)
    • R152 (a 0 Ohm resistor to FLASH_CFG_CSZ)

    The net result is that CS_B_0 in the EVM configuration for SPI Flash is pulled to ground via a 1K Ohm pull-down resistor.  This will be updated in the upcoming DLPC910 data sheet.

     

    Who should control the CSn?

    If using the Xilinx Impact tool over JTAG (J17), then the DLPC910 will control CSn. 

    If using the SPI, when R126, R131, R132, & R133 then the SPI connector J18 will directly control CSn

    FLASH  DIN

    In the EVM Schematics, this pin is controlled by Micro Controller GPIO which is routed also to the DLPC910 pin AA9 which is reserved. can you explain?

    Again, this is a multifunctional pin.  When in JTAG programming mode for the SPI Flash, this is an output from the FPGA to the SPI Flash input.  Otherwise it is a GPIO.

    USB_GPIO15 is not connected in the EVM and is reserved.   

        

    How should I program the flash?

    Please see the linked EVM Guide for the two options to program the SPI flash, starting on page 62.

               

    In the EVM there is option through GPIO or connector: 

    Through JTAG (J17) or the SPI connector (J18).  There is not a GPIO option.
               

    In the Errata it is stated that "End customer will program the SPI flash, either before PCB assembly or via the Xilinx tools after assembly"
    Does it mean by Vivado?

    Please see section 5.3 JTAG Flash Programming of the new EVM Guide on page 62.

    This in the Impact tool NOT Vivado.

     

    If I have an FPGA and a flash (no TI related) to have the SPI shared just use different CSn?

    This is a question you will need to direct to Xilinx.

     

    Do you recommend/use any tool to program it from the [SPI] connector? 

    We have done this using a Cheetah programmer from Total Phase.  The pinout is already compatible with the cable on this programmer.

    I hope this answers the questions that you have concerning the new layout for SPI Flash configuration.

    Fizix

  • Hi Fizix,

    on the DLPC082C schematics (part of the dlpr108.zip package) the cheata programmer connector has two pins 1, 9 for the FLASH_CFG_CDZ. 

    can you help understand why two pins (and populated resistor) are routed to flash CS pin?

    and which one should be chosen?

    adding the schematics screen shotpins 1,9 of samenet

  • Moshe,

    You are correct.  It should still work fine in this configuration, but for clarity, from the Cheetah side Pin 1 is CS2 and Pin 9 is CS1.  The connection to Pin 1 (CS2) can be omitted if desired.

    Fizix