DLP471TP: The power down timing for DLP471TP

Sophie Chen(DLP)

Part Number: DLP471TP
Other Parts Discussed in Thread: TPS65145, , DLPDLCR471TPEVM, DLPA3005

Hi team,

My customer is developing the direct laser platform with DLP471TP and using TPS65145 to offer Vbias, Voffset and Vreset, as our reference design does. I want to whehter we have a strict requirements on the power down timing for these three voltage. Do they need to be 0 at the same time? As I don't have a EVM board with direct laser, I can't measure the power down timing at my side. But on my customer's board, there is some delay between three voltage, and the order is Vrst->Vbias->Voffset.

over 1 year ago

+1 Alexander Chan over 1 year ago

TI__Genius 9540 points

Hi Sophie,

I checked with the team and the power down timings look okay, it is okay for the dmd voltages to not be fully in sync and all hit 0 at the same time as they power down.

What reference design were you referring to?

I noticed on the DLPDLCR471TPEVM formatter board schematic, we use a DLPA3005 and not the TPS65145 to control DMD voltages.

Thanks,

Alex Chan

0 Sophie Chen(DLP) over 1 year ago in reply to Alexander Chan

TI__Prodigy 150 points

Hi Alex,

Thanks for the information. The reference design is NDA resource for direct laser solution. Our EVM is public for LED solution, and my customer is developing direct laser platform, so there is some difference.

Thanks,

Sophie

0 Alexander Chan over 1 year ago in reply to Sophie Chen(DLP)

TI__Genius 9540 points

Hi Sophie,

Thanks for the information. I will close out the ticket. Feel free to reach out if there are any other questions.

Regards,

Alex Chan

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DLP471TP: The power down timing for DLP471TP