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Original question:

DLP4710: DMD_VRESET low level voltage amplitude exceeds the lower limit when the device is loaded

DLPC3479: PAT_RDY Fail

Hiromi Takeda
Prodigy 20 points
Part Number: DLPC3479
Other Parts Discussed in Thread: DLP4710LC,

Tool/software:

Using set of DLP4710LC and DLPC3479.

we are facing a trouble now to see PAT_RDY fail even PROJ_ON is provided.
It fails at a rate of 1 in 500 times.

we can recover by providing PROJ_ON again.

I would like to have the information that 
Is it known ? or do we have any specific reason it fails ?

 

  • 0
    TI__Expert 7140 points

    Hello Hiromi,

    Thanks for reaching out through E2E!

    Could you help me understand a bit more about your setup? What is the firmware version you are using? Are you utilizing the DLPC4710EVM-LC offered through ti.com?

    Best,

    Aaron

  • 0 in reply to Aaron Black
    Prodigy 20 points

    Hello Aaron,

    Thank you for your quick response.

    We are working on the board generated in-house by referring to the EVM circuit diagram.

    firmware version is v8p3p0.

    Regards,

    Takeda

  • 0 in reply to Hiromi Takeda
    TI__Expert 7140 points

    Hello Hiromi,

    Could you please advise me on the your procedure and I will try and recreate this from my end.

    Best,

    Aaron

  • 0 in reply to Aaron Black
    Prodigy 20 points

    Dear Aaron san

    Thank you so much to help me.

    This is our procedure below,

     -------

    set PROJ_ON to LOW

    wait 50ms

    set PROJ_ON to High

    after reset by PROJ_ON, we send parameters to DLPC3479 by I2C,

    set XX to 54h (XX is various value)

    set XX to 98h (XX is Parameters)

    set 04h to to 05h (Operating Mode Select  Internal Pattern Streaming Mode)
    set 00h to 9Eh (Internal Pattern Control)

    and wait PAT_RDY for 500ms 

     ↓

    Usually we can detect PAT_RDY active
    however It fails at a rate of 1 in 500 times.

    If you need more information, please let me know.

  • 0 in reply to Hiromi Takeda
    TI__Expert 7140 points

    Hello Hiromi,

    There is a new firmware release that has multiple bug fixes, I can reach back out after the firmware update is live.

    I will continue to try and replicate this but the software should be available soon and you can test it on your end shortly.

    I will update you as soon as I can!

    Best,

    Aaron

  • 0 in reply to Aaron Black
    Prodigy 20 points

    Great
    I am looking forward to release then

    Thank you

  • 0 in reply to Hiromi Takeda
    TI__Expert 7140 points

    Hello Hiromi,

    Again, I'll keep you updated. Thank you!

    Best,

    Aaron

  • 0 in reply to Aaron Black
    TI__Expert 7140 points

    Hello Hiromi,

    I just discussed with my team member who is releasing the software, the update is not related to PAT_RDY, but it could be worth an investigation if you already have the automation up an running.

    The hotfix would utilize this file dpp3479_dual_ASIC_8.3.1.img

    I would like to understand further what you are defining as 'failing', what voltages are you seeing on the Patten Ready line and are you testing it as close to the controller as possible?

    Best,

    Aaron

  • 0 in reply to Aaron Black
    Prodigy 20 points

    Dear Aaron,

    Thank you for your information.
    As my office will be resumed 19 Aug, I will be back here with answers.

    Again, thank you for your advice.

  • 0 in reply to Hiromi Takeda
    TI__Expert 7140 points

    Hello Hiromi,

    I'm looking forward to hearing back.

    Best,

    Aaron

  • 0 in reply to Aaron Black
    TI__Expert 7140 points

    Hello Hiromi,

    Just as a note, the hotfix has been released as 8.4.0 which is available on the firmware selector tool here - https://software-dl.ti.com/dlp/pico-fw-selector/

    Best,

    Aaron

  • 0 in reply to Aaron Black
    TI__Expert 7140 points

    Hello Hiromi,

    We hope your holidays have been well!

    Please note as we haven't had a response for a considerable amount of time, our automated system with consider this thread resolved and close this thread if not responded to soon.

    Best,

    Aaron 

  • 0 in reply to Aaron Black
    Prodigy 20 points

    Dear Aaron

    Sorry for keeping you wait for long.
    we have been evaluating with dpp3479_dual_ASIC_8.3.1.img, we see the different situation.
    original problem frequency is obviously decreased.
    however, the different phenomenon is happening.

    we are checking what is happening now.

    Anyway, what we can say is the condition is changed by upgrading the dlp fw.

    Thank you for your advice and please keep in touch more.

  • 0
    Prodigy 40 points

    The issue where the PAT_RDY signal fails even when PROJ_ON is provided, with a failure rate of about 1 in 500 times, could be due to several factors. One possibility is a timing or communication issue between the DLPC3479 controller and the DLP4710LC DMD. It's important to check for the latest firmware updates for the DLPC3479, as this could be a known issue addressed by a newer version. Also, review the timing requirements in the datasheet to ensure that the PROJ_ON signal is asserted for the correct duration and within specified limits. Additionally, verify that the power supply is stable, and there are no signal integrity problems or communication errors on the interface between the DLPC3479 and the DLP4710LC.

    Since re-asserting PROJ_ON seems to recover the system, it suggests a temporary glitch rather than a permanent failure. While this provides a short-term workaround, further investigation is needed to ensure long-term reliability. Checking the setup against the datasheet and consulting with the component manufacturer for any known issues or guidance is recommended.

  • 0 in reply to Romer Romszald
    TI__Expert 7140 points

    Hello Takeda,

    What Romer says is entirely true, and there are many possibilities that we can try to solve your issue but you should be utilizing the latest software as more bugs have been removed since 8.3.1.

    Although there are many ways to come to a solution, the most effective solution (I think) will be checking the timing with an oscilloscope for timing glitches. You will want to triggering on PAT_RDY while monitoring other lines accordingly, please start with power lines. With a glitch causing an issue 1 in 500 this will be laborious but should yield a solution.

    Best,

    Aaron