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DLP3021-Q1: FPGA Response Time for DMD Image Switching After SPI Command.

Johns Chuang
Prodigy 220 points
Part Number: DLP3021-Q1
Other Parts Discussed in Thread: TMP411

Tool/software:

Dear Team,

How much time does it take for the FPGA to switch the image on the DMD after receiving an SPI command(0x74)?

Regards,

Johns

  • 0
    TI__Expert 4420 points

    Hi Johns,

    Sorry for the delay.

    I see that the DLP3021/DLP2021 FPGA User's Guide has the following SPI timing diagram and table for you.

    In addition to this, the DLP3021-Q1 Datasheet also has timing specifications for the DMD in Section 6.7. Further information may be found throughout Section 7 for a detailed description of the DMD.

    If this answers your question, please consider checking the "This resolved my issue" button.

    Regards,
    Michael Ly

  • 0 in reply to Michael Ly
    Prodigy 220 points

    Hi Michael,

    I am trying to make the DMD quickly switch between two sets of images, representing single-digit and tens-digit numbers from 0 to 9, to produce the effect of numbers from 0 to 99.
    However, when I issue commands based on the state of FPGA_INTERRUPT, the image switching effect is too slow.

    Therefore, I would like to inquire about the time information from when the FPGA receives the SPI command to when the DMD completes the change, rather than the time for individual signal transmissions. Alternatively, could you suggest the minimum interval between each SPI command?

    Thank you for your help.

    Johns

  • 0 in reply to Johns Chuang
    TI__Expert 4420 points

    Johns,

    Thank you for clarifying. I understand your requirements now. Let me get in touch with a colleague who is more familiar with this, and I should be able to get back to you in a couple of days.

    Thank you for your patience,
    Michael Ly

  • 0 in reply to Michael Ly
    TI__Expert 4420 points

    Hi Johns,

    Johns Chuang said:
    Therefore, I would like to inquire about the time information from when the FPGA receives the SPI command to when the DMD completes the change, rather than the time for individual signal transmissions.

    I believe my original reply does answer your question still. We have given you the clock to data out time and included the datasheet that shows the DMD interface timing.
    This would give you the time the FPGA takes to respond and output data to the DMD plus the time the DMD takes to respond to data reaching it. The interface timing spec should then answer your question about additional time it takes for the DMD to respond to this data. The time it takes a mirror to flip should still be in nanoseconds. In addition to this, your hardware design and layout may affect these timings a bit along with what flex cable, if any, that you use.

    The above image is also taken from the DLP2021 and DLP3021 FPGA user's guide.

    Thank you,
    Michael Ly

  • 0 in reply to Michael Ly
    Prodigy 220 points

    Hi Michael,

    According to the specs, if I send 0x74 (stop) + 0x64 (new address) + 0x74 (start) to the FPGA, which then sends control signals to the DMD, the new image should appear in under 10ms, right?

    Best,

    Johns

  • 0 in reply to Johns Chuang
    TI__Expert 4420 points

    Johns,

    I believe this is the case, but I will verify with my colleague on Monday when we get back into the office.

    Regards,
    Michael Ly

  • 0 in reply to Michael Ly
    TI__Expert 4420 points

    Johns,

    My colleague was able to help me out today, and we have some questions.

    • What kind of application do you have in mind apart from going 0 to 99 as a proof of concept?
    • How many bit planes per frame are you using?

      • 12 bit planes per frame would get you closest to 10 ms if that is your target.

    • Are you using any compression?
    • What time target requirement do you have (I.e., did you need faster than 10 ms?)
    • Are you running at 5 MHz SPI? That is the fastest this interface would go

    Addtionally, the user's guide I linked in my original reply says the FPGA has a 130 MHz clock speed between the the flash memory interface (so that could be one bottleneck -- the time it takes for the FPGA to communicate with the flash memory). You should be able to see if this does affect your system yourself, however.

    Regards,
    Michael Ly

  • 0 in reply to Michael Ly
    Prodigy 220 points

    Hi Michael,

    Thanks for your help. Here’s the information:

    1. My goal is to project the temperature from the TMP411 using the DMD and to explore projecting letters as well.

    2. The FPGA bit planes are fixed at 20 bits, right? I don’t plan to change the RGB884 setup.

    3. The images are generated by DLPComposer, with RLE compression as the only compression.

    4. Sorry for the confusion, but 10 ms is not my target. According to the .img structure from Composer, the images are at 25 Hz, so the DMD updates every 40 ms, correct?

    Given this, my target should be 40 ms. I’m trying to ensure that each new image has a new Video Start Address to see how many letters/bit planes I can use.

    5. Currently, we’re using 250 kHz SPI, but we’re experimenting with 5 MHz.

    Thanks again for your assistance.

    Johns

  • 0 in reply to Johns Chuang
    TI__Expert 4420 points

    Hey Johns,

    Thanks for the information. Please allow a few days for me to get back to you. I've unfortunately been sick all day and may have to take tomorrow off.

    Regards,
    Michael Ly

  • 0 in reply to Michael Ly
    Prodigy 220 points

    Hi Michael,

    I’m sorry to hear you’re not feeling well. Wishing you a speedy recovery. Take care!

    Best,

    Johns

  • 0 in reply to Johns Chuang
    TI__Expert 7390 points

    Hey Johns,

    Please give Michael a little bit to get over his sickness, he'll respond when he can.

    Best,

    Aaron

  • 0 in reply to Aaron Black
    Prodigy 220 points

    Hi Aaron & Michael,

    Thank you for your assistance. I believe the issue might be with the goals set for my experiment.

    I have reviewed and simplified my experimental method. I am now using only FPGA’s VCM_LOOPCONFIGS_FID and VCM_TOGGLE_CONFIGS_FLD to achieve rapid switching between the images of VCM_START_ADDR1 and VCM_START_ADDR2. I believe this should be the fastest image switching speed achievable by the FPGA architecture without considering external SPI.

    However, the results are still not ideal. Therefore, I would like to ask if it is possible to increase the speed of switching between VCM_START_ADDR1 and VCM_START_ADDR2 using only DLPComposer and an external MCU, without changing the FPGA program?

    Thank you again, and I wish Michael a speedy recovery.

    Best,

    Johns

  • 0 in reply to Johns Chuang
    TI__Expert 4420 points

    Hi Johns,

    Thanks for the additional information and good wishes. I will be back into the office tomorrow to pick things back up. Please allow me some delay as I catch up on missed emails and other events. Your patience is greatly appreciated,

    Best regards,
    Michael Ly