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Original question:

DLPC410: Interface information between cy7c68013 and APPSFPGA

DLPC410: the issue about glitches of the image displayed on DMD

jing.miao
Prodigy 110 points
Part Number: DLPC410

Tool/software:

Hello,
        We have redesigned a development board, replacing the Virtex 5 AppsFPGA chip with a Kintex 7 chip while keeping the DLPC410 chip unchanged. The entire design references TI's EVM (PWB 2510300 REV F). Currently, the basic functionality is working, but there is an issue where the left half of the image displayed on the DMD shows glitches (see attached image), which we suspect is related to the AB bus within the ABCD bus.
We would like to ask:
1. Is this issue likely caused by hardware design or manufacturing process problems?
2. If it is a design issue, in which specific stage might the problem have occurred?

Thank you.

Jing miao

  • 0
    TI__Guru 52225 points

    Hello Jing,

    This could be on either the input data side or the output data side.  The issue appears to be related to the AB bus as you suggest.

    I would check the trace lengths on both input and output of the AB bus, the clock input relative to the input and output data lines of the AB bus.  

    For the DLPC410, the input clock and the data should be in sync (i.e. the edges should be lined up.  The DLPC410 internally delays the clock 90 degrees.

    For the output, the clock should be 90 degrees from the data.  Check the DLP95000 data sheet on the LVDS setup and hold information.

    This could also  be a poor connection on one or more of the LVDS input or output lines resulting in capacitive effects.

    Try some other patterns to see if it is changes the behavior.  For example try a diagonal line on the AB bus.  Try a circle(s) to see if "ghosting" occurs.

    Please post back pictures of the results.

    Fizix

  • 0 in reply to Fizix
    Prodigy 110 points

    Hello Fizix

    We sent circles and diagonal lines to the DMD, and the results are shown in the figure below. The observed phenomenon is similar to the pattern of squares.

    Jing. Miao

  • 0 in reply to jing.miao
    TI__Guru 52225 points

    Hello Jing,

    This signature is typical of capacitive issues on the LVDS interface.  In this case bus A and B.

    I would check the clock and the alignment on the input and the outbound clock to the DMD and at the DMD.

    Fizix

  • 0 in reply to Fizix
    Prodigy 110 points

    Hello Fizix，

    We would like to test and capture the clock and data signals between the DLPC410 and the DMD. However, on both our custom board and TI’s development board, the DLPC410 and DMD are directly connected via traces without accessible test points. Without access to these signals, we cannot troubleshoot potential issues.

    Our questions are:

    1. How did TI historically measure the clock signals between these components during your development?

    2. For existing development boards (with designs similar to TI’s), how can we access these signals?


      Could you provide any methods or suggestions for capturing these signals under these constraints?

    Jing. miao

  • +1 in reply to jing.miao
    TI__Guru 52225 points

    Jing,

    For connections to the DMD there are via's behind the pads that connect to the interposer.  The layout files available on ti.com should help you locate these along with the pinout from the DMD data sheet.

    The connections between the APPS_FPGA and the DLPC410 are indeed more difficult because some traces are buried and only the vias to the FPGA solder pads are accessible and the expoxy coating has to be scratched off.

    Judging from the way the patterns are ghosted this would likely be a clock line on the A or B bus.

    Fizix