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Original question:

DLPC410: the issue about glitches of the image displayed on DMD

DLPC410: issue about the phase on data bus and clock bus

jing.miao
Prodigy 110 points
Part Number: DLPC410

Tool/software:

Hello,

We now have a relative question with the previous issue(https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1470109/dlpc410-the-issue-about-glitches-of-the-image-displayed-on-dmd). According to your suggestions, we conducted tests on the A B C D bus and observed discrepancies between the B bus and the other buses. The differences among the A C D buses were minor, suggesting potential issues with the B bus. We will inspect the circuit routing of the B bus.

Based on the test results, a new issue was identified: Between the APPSFPGA and DLPC410, the phase difference between the clock and data signals on the C bus is nearly 0°. However, between the DLPC410 chip and the DMD, the data lines exhibit a phase delay of approximately 270° relative to the clock lines (or equivalently, the clock lags the data lines by 90°). Similar behavior was observed on the A and D buses (see figure below: yellow represents clock signals, red represents data signals).

Notably, the DLPC410 documentation specifies that data bus signals should lag clock signals by 90°. Despite this apparent discrepancy, the DMD displays images normally via the A C D buses.

Now we need to verify: Could there be timing or routing issues between DLPC410 and DMD on buses A C D?

Jing, Miao

  • 0
    TI__Guru 52450 points

    Jing,

    Which image is the B and which is from A,C,D?  The clock does not look very clean in the second image clock does not look as clean as the first image.

    Fizix

  • 0 in reply to Fizix
    Prodigy 110 points

    Fizix，

    Yes, the waveform in the second image is not clear, which might be related to our testing equipment, possibly due to high noise levels.

    Both images show results from the C bus (similar to A and D buses). The first image displays waveforms between the APPS FPGA and DLPC410, while the second image shows waveforms between DLPC410 and DMD.

    According to DLPC410 chip specifications:

    1. In the first image, the phase difference between data and clock should be 0° (actual measurements match theory).

    2. In the second image, data should lag clock by 90° (measurements show clock lags data by 90°, with yellow representing clock and red representing data).

    We are concerned about potential layout issues with the ACD bus (despite normal DMD display performance). 

    Jing, Miao

  • 0 in reply to jing.miao
    TI__Guru 52450 points

    How does the B bus DLPC410 to DMD look?

  • 0 in reply to Fizix
    Prodigy 110 points

    Fizix,

    The first image displays waveforms between the APPS FPGA and DLPC410 from B bus, while the second image shows waveforms between DLPC410 and DMD.  The phase difference between the APPSFPGA and DLPC410 is abnormal.

    Jing, Miao

  • +1 in reply to jing.miao
    TI__Guru 52450 points

    Jing,

    The second image seems to pinpoint your issue.  That needs to be lined up to look like the inputs on A, C, & D.

    I am assuming this is code you wrote, or a board of your own design.

    Fizix