DLPC410: Bitstream Configured for Faster CCLK

Hi Fizix,

Thanks for the quick reply.

I'm talking about the SPI Flash file from TI for DLP410C.  Our DLP410 is Mode configured for Master Serial (MD[2:0]==1).

It takes about 4 seconds to configure.

I'm not requesting or asking to change the source but rather that TI use the BitGen -g ConfigRate and regenerate the bit file from the project's NCD file with 16 MHz CCLK frequency.

Or, can you provide the NCD file?

Thanks,

Tim

TIm,

I will have to discuss this with our FPGA team.  Typically this is not something we provide.

Fizix

Hi Fizix,

That's awesome and thanks for checking with your team.

Tim

TIm,

I am sending you a friend invite.

Fizix

Fizix,

I accepted.

Tim

Thank you.

Tim,

I got an opportunity to speak to our FPGA team today.  They need to look into this to see what they can do and if they are willing to sign up for this.  No promises.  Please allow a few more days.

Fizix