I'm experiencing some problems triggering the DLPC200 that I'm hoping someone can help with.
First a brief background on our setup. I'm using this system in Structured Light mode. Our setup is loading 120 images into memory and then selecting a varying amount of them to display in a sequence. For example, we might pick six images to display when triggered. We are driving the controller with an external trigger on Port2_Trig_In. Our trigger pulse width is typically 15uS but we've tested with a width of as little as 66ns and as much as 1ms. Since we are using this in structured light mode only and not video mode we do not use port1 at all and on port2 only the trigger and clock signals are hooked up. All other signals except VSYNC and HSYNC are connected to ground via a 10k resistor. The sync signals are left floating. We are using only one of the LED enable signals to drive a custom LED drive circuit (specifically LED_GRN_EN). We are using version 2.20 of the DLP firmware.
We are seeing a couple of different problems with this setup. In one instance we will send a series of six pulses, which we see get to the DLP controller, but the LED Enable will only fire five times. And when this happens one of the images in the sequence is skipped. So if I set the image order to display the first six images normally I would see images 1, 2, 3, 4, 5 and then 6. But in this case I might see 1, 2, x, 5, 6 and 1. Which image in the sequence that is skipped can vary. In this case the controller is definitely not triggering because I can see that the DMD is still displaying the last bitplane of the previous image and yet it will still skip ahead as though I had triggered it twice.
The second scenario is similar to the previous except that the LED enable does fire each time and the DMD displays unique images each time. But again every now and then I see it skip one of the images. It is as though the DLP controller thinks that it was getting two trigger pulses where it should only get one.
These problems don't occur every time an image sequence is triggered. But I might run though this sequence of images 20 or 30 times and then see a failure.
1) What are the timing requirements for the trigger pulse? I'm feeding in a 1.8v signal that is between 66ns and 1ms long.
2) Does this trigger need to be syncronous to the Port2_CLK? I am using a 75MHz oscillator for the clock but the trigger is being generated elsewhere by an FPGA.
3) It appears that the controller is looking for an edge on the trigger (rising or falling depending on how you configure it). Can you confirm this?
4) Is there any rise or fall time requirements that need to be met?
5) What is the voltage threshold for the trigger? If I have some ringing or ripple noise on my trigger, when am I in danger of re-triggering the controller?
6) Are there any conditions that you are aware of that can cause the DLP controller to get confused and miss a trigger but still recover when it is next triggered?
These problems are blocking problems for us so every effort that you can make to help out is greatly appreciated. Please let me know if I can provide any additional information or run any tests for you.
Best regards,
Tim
