DLPC200: about DLPC200 parallel memory interface

Hi H.U,

Thanks for your detailed question. If you could give me until early next week to get you an answer, I would appreciate it.

-Paul

Hi H.U,

This information is taking a little longer to track down, so if you could give me until next week, I would appreciate it. I am traveling this week so I won't be able to work on this until I return.

Thank you for your patience!

-Paul

Hi Paul-san

Thank you for your correspondence.
I am looking forward for your response.

Best Regards,
H.U

Hi Paul-san,

Please let me ask one more question.

Q5: Is it possible to input the OE signal with an inverting circuit to the FLASH_SRAM_RDY terminal of DLPC200?
       Can I use the OE signal as a substitute for the WAIT signal?

Best regards,
H.U

Hi H.U,

Q1: I want to use MT28EW01GABA1HPC memory instead of JS28F00AP30BF. Is the firmware of DLPC200 compatible?

I am still confirming this information.

Q2: The WAIT signal of JS28F00AP30BF is connected to FLASH_SRAM_RDY terminal. If MT28EW01GABA1HPC is used, can I connect the RY/BY# signal of this memory to FLASH_SRAM_RDY?

We are not experts on these devices, but it does appear that the RY/BY# signal is similar to WAIT.

Q3: Is FLASH_SRAM_RDY terminal allowed to be pulled up? Because the RY/BY# signal needs to be pulled up.

The FLASH_SRAM_RDY terminal is allowed to be pulled up, it is an input LVCMOS port.

Q4: I think that the minimum value of the tAVAV described in the following document should be specified, but this document is described the maximum value. Is my thinking correct?

I understand why you think this. I will ask for more clarification on this point.

Q5: I'd like to verify that I can meet the requirements of tPHQV(Max:150ns) on my custom board. So, I want to know /RST the minimum time from /RST goes high to /CE goes low.

From the diagram you attached, the time you are looking for can be calculated. I get 40ns. tPHQV - tAVQV = 40ns.

Q6: Is it possible to input the OE signal with an inverting circuit to the FLASH_SRAM_RDY terminal of DLPC200? Can I use the OE signal as a substitute for the WAIT signal?

I think not because it is important for the DLPC200 to have the memory report back when it is actually ready to accept more data and is done writing.

Thank you,

-Paul

Hi Paul,

Thank you for your reply.
For the handling of the WAIT signal I would like to wait for your answer as to whether the firmware is compatible or not.
I am concerned about the availability of JS28F00AP30BF memory. I hope that other recommended Flash memory will be presented.


>From the diagram you attached, the time you are looking for can be calculated. I get 40ns. tPHQV - tAVQV = 40ns.

I think that 40ns is maximum requirement. I want to know minimum requirement.

Best regards,
H.U

H.U,

Q1: I want to use MT28EW01GABA1HPC memory instead of JS28F00AP30BF. Is the firmware of DLPC200 compatible?

Can you please contact Micron and see what they recommend as far as pin compatibility with the JS28F00AP30BF? Their expertise will be useful here and they will be able to give you good advice on whether or not these parts are interchangeable.

You may also consider contacting Numonyx to see if they have a replacement device for the JS28F00AP30BF if availability is bad.

Q4: I think that the minimum value of the tAVAV described in the following document should be specified, but this document is described the maximum value. Is my thinking correct?

tAVAV should be a maximum value because the flash needs to make information available within a certain time so that the controller can read it. 

Q5: I'd like to verify that I can meet the requirements of tPHQV(Max:150ns) on my custom board. So, I want to know /RST the minimum time from /RST goes high to /CE goes low.

I'm sorry that I misunderstood your question. From the datasheet, "to perform a write operation, both /CE and /WE are asserted while /RST and /OE are deasserted. During a write operation, address and data are latched on the rising edge of /WE or /CE, whichever occurs first"

As long as /RST occurs before /WE or /CE, and it takes no more than 40ns to do that, your device should operate within spec. We do not have a minimum time specified at this point. If I learn something different I will post back.

Thank you,

Paul