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DLPC200: duty cycle in LVDS clock signal

Part Number: DLPC200
Other Parts Discussed in Thread: DLP5500,

Dear,

I've made application board using DLPC200 and DLP5500.

working is good so far but some question as below picture is screen shot in LVDS Clock of DLP5500 board. but duty cycle is different as i marked "A", "B".

i think since it is clock signal, it must be fixed but marking A is longer than marking B. i have to verify it is normal signal or there are some problem.

because i have to prepare mass production using this device.

please help it is normal signal or not.

if you can't check below picture, please check attached the file.

thanks.

  • Kim,

    The waveform you show is not normal, it should be approximately 50%.  However, since your system seems to be working fine, I would check the way you have it connected up to your scope.   Are you using a differential probe or a single ended probe? 

    If single ended grounded then you can use 2 channels with one connected to CLCK_P and the other connected to CLCK_N and then create a "math channel" that is (Ch1 - Ch2).  You need to look at the differential signal, not P or N alone.

    Fizix