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Linux/DLPC6401: Input Configuration of DLPC6401

Part Number: DLPC6401
Other Parts Discussed in Thread: SN65DSI83,

Tool/software: Linux

Hello Support team,

We are working on one product design, where we need help from your side.

For this product, we are using SN65DSI83 for DSI-to-LVDS output and the output from SN65DSI83 is given to DLPC6401.

1. For the video parameters like Horizontal, Vertical Sync, etc... we need to set these parameters according to DLPC6401 controller for resolution of 1280*800.

We set the video parameters as follows :

1. CHA_ACTIVE_LINE_LENGTH = 1280 or 0x500
2. CHA_VERTICAL_DISPLAY_SIZE = 800 or 0x320
3. CHA_HSYNC_PULSE_WIDTH = 80 or 0x050
4. CHA_VSYNC_PULSE_WIDTH = 9
5. CHA_SYNC_DELAY = 32
6. CHA_HORIZONTAL_BACK_PORCH = 40
7. CHA_VERTICAL_BACK_PORCH = 7
8. CHA_HORIZONTAL_FRONT_PORCH = 40
9. CHA_VERTICAL_FRONT_PORCH = 7
10. LVDS_CLK_RANGE = 62 MHz to 87.5 MHz
11. DSI_CLK_DIVIDER = 3
12. CHA_DSI_LANES = 4
13. CHA_DSI_CLK_RANGE = 430 to 435 MHz
14. CHA_24BPP_MODE = 24bpp mode (format 2)

  but in DLPC6401 data sheet -Section 7.3.1.5  they have mentioned different data for video parameters.

So we need to know about video parameters for 1280 x 800 resolution that we have to configured  to send data to DLPC6401 controller.
1. Horizontal and Vertical Sync Pulse
2. Sync Delay for Horizontal and Vertical Sync
3. Front and Back porch for Horizontal and Vertical Sync

Thanks,

Nilesh Patil

  • Hi Nilesh Patil,

    In the DLPC6401 controller datashseet Section 7.3.1.5 Source Input Blanking - it mention the minimum blanking timing this is applicable both RGB 30-bit parallel port or LVDS (FPD) port; for the LVDS port the only limitation being the max pixel clock on this port is upto 90MHz only, so refer to the Source Input Blanking section, make sure your video output meeting the minimum blanking time and the pixel clock is < 90MHz it should work just fine.

    Regards,
    Sanjeev

  • Hello Sanjeev,

    Thanks for your response.

    1.  Can we change the Blanking time as per the different resolution of LVDS.

    2. In DLPC6401 which i2c registers are to be configured for LVDS input as in programmer guide for DLPC6401 there are various registers mentioned.

    Thanks,
    Nilesh Patil

  • Hi Nilesh,
    1. Yes, as long as you ensure the minimum blanking timing specs met.
    2.
    The below are the basic register for you to get source detected.
    Register[0x02] - Input data format
    Register[0x17] - FPD Clock range
    Register[0x05] - FPD mode select
    Register[0x19] - FPD polarity // required if it is different from the default
    Register[0x00] - Set source to FPD // 0x03

    After this you can play with various control options as provided in the PG.
    Regards,
    Sanjeev