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DLPC910: LVDS input termination (Datasheet Rev D)

Part Number: DLPC910


I have noticed the DLPC910 data sheet update to revision D from Sep 28th 2020.

It states "Updated Description section for DDC_DCLK_(A,B,C,D)_DP(N,P), DDC_DIN_(A,B,C,D)(1-15)_DP(N,P), and
DVALID_(A,B,C,D)_DP(N,P) from "100-Ω internal LVDS termination." to "100-Ω external LVDS termination

This change would need a redesign of custom boards. And even the reference design TIDA-00570 has no external termination.

Could this change be reverted? If not, then which chip revision will change termination definition from internal to external?

Thanks for clarifying this.

Best Regards - Frank

  • Hi Frank,

    There is no actual change to the design.  It was discovered that this had not been properly implemented in the FPGA design.  This was only a documentation stating that it is "required".  If your design was working it should continue to work.  Technically it should be done.  Very sorry for the inconvenience.

    There are currently no plans for further revisions to the DLPC910.