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DLP9000X: No image on the DMD when we try to Driver it

Part Number: DLP9000X
Other Parts Discussed in Thread: DLPC910

Hello,everyone,

We tryed to drive the DLP9000X DMD,but failed. When I load the data pattern into the dmd,nothing exist on the dmd。

1.ECP2_FINISHED status is correct(High) when I power on our pcb driver board .

2.VLED0 & VLED1 status are correct.

3.I can get DMD_TYPE(3:0) = "1111" and DDC_VERSION(2:0) = "010" through apps fpga debug tool(Xilinx ISE Chipscope)

4. After downloading the apps test file into the apps fpga, I find the RST_ACTIVE's status is not correct(HIGH->LOW,But I didn't load anything into the dmd ).

5. I load the data into dmd(load 1600 row and then global reset ),but nothing on the dmd.

What Can I do next,and How can I debug? 

Thank you !

  

  • Hello Tony,

    We presume that you are using the DLPC910 controller to drive the DLP9000X DMD.  It looks like it is reading the DMD correctly and returning "1111".  

    In 4. you mention that RST_ACTIVE is not correct.  Please clarify.  Do you mean that it is High rather than low?  Also is this apps test file from TI?

    In 5. you mention a global reset. Then see the DLPC910 data sheet section 7.4.4 Mirror Clocking Pulse especially the paragraph immediately following Table 7-13. DMD Block Load Time about sending NoOps after initiating a global reset.  Also what is RST_ACTIVE doing during the assertion of Global Reset.

    Fizix

  • Hello,Fizix,

      Thanks for you reply。I found a bug in my driver board yesterdy, VBIAS/VOFS/VRST didn't work well,Now,I fix the bug ,and VBIAS/VOFS/VRST work well now, but still a problem when I try to load then data into entire DMD, it seems something on the DMD,but only some rows(maybe 100~200 rows) have image,and the image seems wrong .as show below

    I try to simulate drive code, found nothing strange.as shown below 

    #1 load data 

      

     DCLKIN = 400MHZ, DVALID low for last two clock cycles in a row(a row have 20 clock cycles,and Dvalid low at 18th clock cycle,and be low until next row begin).

    #2 load data complete

    the row increase to 1599,and then stop loading data 

    3.Global reset 

    #4 send no-op cycle 

    after global reset,I send no-op row cycles unitil RST_ACTIVE goes low, And I Found RST_ACTIVE goes low(From High to Low) indeed 。

    So,what can I do next to fix the problem,Thank u。

  • Hello Tony,

    Are you taking DVALID low for the last two clock cycles of each row cycle?

    Is it possible to show what should be showing?  It looks like only one block correctly received a "Mirror clocking pulse"  i.e. mirror reset.

    Is it possible to get a little bit closer of an image of the part that is showing?

    Are you using row addressing or automatic row increment mode?

    Fizix

  • Hello,Fizix,

        Thanks for your reply .

    1、Yes。I take DVALID low for the last two clock cycles of each row cycle,and take DVALID high at the beginning of next row cycle 

    2、The image is drawed by photoshop,the size is 2560*1600, the image is composed of several lower-case letters(Our company's logo)。

    3、Yes.I use row addressing mode, row will be increased at every beginning of row cycle(the initial value is 0,and increased to 1599 )。

    So,I don't know why it looks like only several rows correctly received a mirror clocking pulse .

    Thanks you again.

  • Hello again Tony,

    I would check your row address and row mode lines to make sure the values are correct.  This could be a row address issue.  

    I would try changing to automatic increment (where the DMD automatically increments the row counter internally.  The only requirement is to send the command to go to the beginning row.  Thereafter, you send the mode that says auto-increment and send all the rows.  No address is required.  If the whole image shows then there is a signal issue or something wrong in the address portion.

    Fizix

  • Hello Fizix,

    Thanks for your reply again!

    I try to use automatic increment mode(ROWMD= 01,ROWAD = all 0's),and keep the value unchanged。

    I found something different as before。 It look like the part of image “”MOVE“” from DMD's top to Bottom. As shown below

    I doubt if row control leads to this problem,but don't know how to troubleshoot it 。

    looking forward to your reply .

    Thanks again .

    Tony 

  • Hello Tony,

    This suggests an issue of some kind with electrical interface to the controller board with the row address lines.  I would check them carefully with a scope if you can access the signals through via's or resistors ends to make sure that they are right.

    It does not appear to have flipped (top to bottom) the part of the image that appears, only moved it down the DMD.

    Fizix