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DLPLCRC410EVM: Inquire about frame rate

Part Number: DLPLCRC410EVM
Other Parts Discussed in Thread: DLPLCR65NEVM, DLPC410, DLP9500, DLP650LNIR

Hello Team,

According to user manual, it guarantee 32k frame rate on DLPLCR65NEVM.

However, I found the max frame rate is about 6.8Hz when using GUI without giving dmd delay time.

This is the setting.

This is the output signal shown on oscilloscope.

I give dmd with two images(1 black, 1 white), and GP output is 1 and 0 respectively. That mean the real freq should be two time as shown on oscilloscope.

Please help me figure out the problem.


  • Table 1-1 of the DLP Discovery 4100 Development Platform User’s Guide indicates that the DLPLCR65NEVM is capable of 10,800 Hz Max binary pattern rate in global reset mode; or 12,500 Hz max binary pattern rate in Phased Reset mode.

    The manual also indicates in section 3.2 DLP Discovery 4100 Operation: The DLP Discovery 4100 Development Platform is capable of operating at about 7-10 DMD frames per second (DMD dependent) when connected to a host system’s USB 2.0 port.

    Please see this post for further comments on the topic of the DLPC410 controller and the EVM.

    This post is related to the DLP9500; but the same comments apply to the DLP650LNIR DMD as well. The pattern rates may be a bit different, but the overall comment still applies:

    • To achieve this speed you must write your own APPS_FPGA code that pro grammatically generates full image data at the required speed, or you must instantiate a Memory Controller in the APPS_FPGA (Xilinx MIG (Memory Interface Generator) and populate the memory slot.
    • Or you can write APPS_FPGA code to accept input data from the two EXP connectors that you route through to the DLPC410 controller.