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DLP7000: Additional information needed

Renan Santos Adriano
Genius 16540 points
Part Number: DLP7000
Other Parts Discussed in Thread: DLPC410

Hello Team,

My Customer would like to ask  some question about the DLP7000 (DLP 0.7 XGA 2x LVDS Type A DMD). (1) How high is the sample rate of the micro mirrors translating the bit sequence into tilt movements? (2) Do we have a schematic signal path from the bit sequence to the optical (modulated) signal?

Regards,

Renan

  • 0
    TI__Mastermind 43165 points

    Hello Renan,

    I think there is a bit of misconception about what the DMD does.  The DMD is only a binary device.  The user microcontroller for this device must do the bit sequence translation.

    The DMD is loaded one row at a time which if run at 400 MHz (at DDR that is 800 Msamples/second per line) over 32 lines and 16 clocks = 1024 bits.  So the bandwidth during loading is 256 Msamples/second).

    So the row load takes 40 ns.  Over 768 rows that is 30.72 microseconds to load, but then a mirror clocking pulse (mirror reset) must be issued, either per block or at the end of the device load (i.e. phased vs global). This is the binary pattern rate shown in the data sheet.  NOTE: The DMD micromirrors do not show the pattern until the mirror reset is received.

    For more information on the mirror resets and other loading information see the DLPC410 controller data sheet.

    The DLPC410 controller that drives the DLP00 has a one row latency (40 ns).

    Fizix