https://e2e.ti.com/support/dlp-products-group/dlp/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1656823/dlp4620spguq1evm-custom-color-sequence-g-g-g-for-dlp4620spguq1evm-to-achieve-higher-brightness/6389196Fri, 19 Jun 2026 16:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:be63caf8-79a8-490e-853e-89e4edf32b9eJason ThompsonHello Yoshiki-san, Good news is that we have a method for doing this. You need to also get the https://www.ti.com/tool/DLP4621Q1EVM . This EVM is for headlight configuration, which is a mono-white LED. However, it would also drive the green LED 100%. The DLP4620S configuration has many checks in place to ensure that RGB is always toggling, so it is not easy to use it. Therefore, you should get the DLP4620SPGUEVM and DLP4621EVM. Then you can connect the Main board and the LED driver board from the DLP4621EVM onto the PGU. Then, connect the Green LED only to the driver board. This will allow you to drive the Green LED 100%. Please take a look at the EVMs and let us know if you have any questions. Jasonhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654839/dlpa3005-dlpa3005-s-illum_bw_bcx-register/6389041Fri, 19 Jun 2026 14:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:18c02478-d236-4255-8fdf-87b050d11edcKevin RiveraHello Tanabe, We are currently looking into this manner, I will follow up when I have more information! Thank you, Kevin Riverahttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1656823/dlp4620spguq1evm-custom-color-sequence-g-g-g-for-dlp4620spguq1evm-to-achieve-higher-brightnessFri, 19 Jun 2026 05:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a165a2dc-52ad-4cd5-8c04-54aa17266974Arita YoshikiPart Number: DLP4620SPGUQ1EVM Other Parts Discussed in Thread: DLP5530S-Q1 Dear TI Support Team Thank you very much for your continued and exceptional technical support. Thanks to your help, our previous evaluation regarding the lens progressed very smoothly, and we truly appreciate your dedication. Today, I would like to consult you regarding a new experimental approach using the DLP4620SPGUQ1EVM. To achieve even higher brightness for our project, we are interested in operating this PGU in a Green monochrome display mode . Specifically, our idea is to modify the standard time-division RGB driving sequence RGB into a green-only sequence ( GGG ). By maximizing the emission time of the green LED, we hope to significantly increase the overall brightness. Previously, during our discussion regarding the environmental resistance of the DLP5530S-Q1 (&quot;DLP5530S-Q1: Questions about environmental resistance&quot;), TI kindly provided us with dedicated software (such as custom firmware) , which was an outstanding and highly appreciated support. For this DLP4620S project as well, we would like to know if it is possible to receive similar software-level support or custom tools from TI to facilitate our high-brightness experimentation. Could you please advise us on the following three points based on the device specifications and capabilities? [Questions] Software Support for Color Sequence Modification (G/G/G): For the DLP4620S controller IC, would it be possible for TI to provide dedicated software or custom firmware to change the LED driving timing from RGB to GGG (Green monochrome)? Alternatively, is this a specification that users can modify on their own using existing configuration tools like DLP Composer? Hardware Constraints (LED Driver &amp; Power Supply): If we software-modify the sequence to triple the green LED emission time, are there any hardware-level constraints—such as Duty Cycle limits on the LED driver/power lines or thermal management thresholds—that might trigger errors or protection features? Similar Past Cases or Recommended Approaches: Are there any precedents within TI or with other customers where an automotive DLP was converted to a specific monochrome color (such as green) to enhance brightness? If so, we would highly appreciate any recommended procedures or alternative approaches you could share. We would be very grateful for your insights on whether this high-brightness approach is feasible. Thank you very much for your time and continued support. Best regards,DLP4621Q1EVMDLP4620SPGUQ1EVMDLP5530S-Q1Aerospace &amp; Defensehttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654839/dlpa3005-dlpa3005-s-illum_bw_bcx-register/6388533Fri, 19 Jun 2026 03:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a5a93ead-f7fb-4b03-af20-be2dff5e7c80Tanabe MasakiSomeone please respond.https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6388337Thu, 18 Jun 2026 21:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7a4ebbcf-1d5d-43fa-aaf4-d80a3afd8342Aaron BlackHello Zhihao, 36h and 37h is correct. If you export the file as a batch file, this will show the full command that is sent - but only the write commands. For troubleshooting, you can add 100ms delays, but 5s is not necessary. Best, Aaronhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1656273/dlp2010nir-mems-plm/6388328Thu, 18 Jun 2026 21:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8b5745e1-1a71-426b-96b1-265d2d55f4d0Aaron BlackHello! Thank you for coming to E2E about this question! We currently do not have any PLM released on ti.com, but we have information available on an external page here . Could you please explain what application this is going to be utilized in? Best, Aaronhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654838/dmd-diffraction-efficiency-calculator-access-to-the-diffraction-efficiency-calculator/6388314Thu, 18 Jun 2026 21:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1b2312fe-279c-4735-a21c-aaa69ff1a125Aaron BlackHello Julia, Our Digital Micormirrors (DMDs) are a diffraction grading because of the pixels and their tilt. These pixels only tilt to 2 different states - &#39;On&#39; or &#39;Off&#39;. The blazing conditions are where the diffraction orders are seen. Best, Aaronhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1656689/dlpdlcr4710evm-g2-inquiry-about-dlp4710-evaluation-modules-for-scientific-imaging-applicationsThu, 18 Jun 2026 14:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:deb693b4-3b22-4db4-9fbc-5498d6bf3441ArTzyPart Number: DLPDLCR4710EVM-G2 Other Parts Discussed in Thread: DLP4710 , DLP4710EVM-LC , Hi Experts, We&#39; like to ask assistance on this query from myTI user, working in the field of optical and microscopic imaging: We are currently considering the use of the DLP4710 chipset for a scientific imaging system and would appreciate your guidance in selecting the most suitable evaluation module. In particular, we would like to understand the differences between the DLP4710EVM-LC and the DLPDLCR4710EVM-G2 . Could you please clarify their respective purposes, key features, and the functionalities each platform supports? Our intended application involves optical and microscopy-based imaging experiments, including but not limited to structured illumination and dynamic pattern projection. We would be grateful for any recommendations regarding which solution would be more appropriate for research applications in these areas. Thank you very much for your time and assistance. We look forward to your advice. Regards, Archie A.DLP4710DLP4710EVM-LCDLPDLCR4710EVM-G2https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6387778Thu, 18 Jun 2026 14:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1ece6ea9-015c-4ff6-bdee-1d909cce2299zhihao dengDear Aaron, According to your suggestion, I checked the logs of TI_GUI. Currently, this board doesn&#39;t have a USB-to-I2C module, so I can&#39;t directly connect this circuit board to the host computer. However, I have a projection module that others made by imitating TI_EVM&#39;s DLPA3005 + DLPC3479_dual + DLP4710LC. But the firmware is not the latest version; it&#39;s 8.1.11712, and it can be correctly connected to TI&#39;s host computer. The picture of the command log is shown as follows, which realizes one cycle of the system. Currently, I&#39;d like to consult you on the following questions: 1. Is it correct that the write address of I2C is 1Bh (7 bits) + h0 (1 bit) = 36h (8 bits), and the read address is 1Bh (7 bits) + 1h (1 bit) = 37h (8 bits)? 2. In the log interface of TI_GUI, the read and write addresses can&#39;t be seen. Only the of meaning the commands can be seen, and the write addresses of the commands can&#39;t be seen. 3. I added a 500ms delay after the commands for starting the internal mode in the FPGA. I even added a 5s delay after the 98 command. Compared with the previous situation, the left side is now completely black. But it&#39;s still not normal. May I ask how to troubleshoot the problem now? I&#39;m looking forward to your reply. Thank you！ best, Zhihaohttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6386740Wed, 17 Jun 2026 21:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:43c80d92-3954-40a7-9e2f-ce870ac8d77bAaron BlackHello Zhihao, If you&#39;re seeing no issue in external mode but as soon as you change the mode to internal mode, this indicates that the internal mode is having an issue. It likely is not an issue with your system. U18 and U16 from our design (SPI Flash) is also W25Q64JVSSIQ, there should be no difference. I would highly recommend you utilize the &#39;Command Log&#39; from the GUI after testing the commands - this has all and more commands for what is necessary in the order that it is performed. Here is the order of commands I&#39;ve sent to a DLPC3478 controller EVM just as an example: W 36 9E 01 00 W 36 98 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 W 36 92 02 00 00 00 00 W 36 92 03 00 00 00 00 W 36 90 02 W 36 94 02 W 36 05 04 W 36 9E 00 FF Try swapping the #1 and #2 - ensuring the pattern has stopped beforehand, then loading the pattern. Best, Aaronhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1651808/dlp3021-q1-follow-up-on-fpga-initialization-issue-on-dlp3021-q1-vs-dlp2021-q1/6386675Wed, 17 Jun 2026 20:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e26a2e7a-aea7-4215-b268-83068ea5c5c8Jason ThompsonHi Johns, Thanks for the feedback. These experiments at least ruled out the power up and brown out as the issue. For the sequence abort, can you read this register from the control program? I think it may not be an option in the customer version. If not, would you be able to read this register from your MCU? The register is available, but the control program may not support it. We had some discussion today about what might cause this issue. We are thinking that maybe there is something marginal in the video data timing, for which the controller locks up. This is the reason for checking the seq abort. One idea / experiment would be to change RGB duty cycle for the same video content and see if this changes the behavior. The idea would be to modify the RGB duty cycle to something like 33/34/33 (just as an experiment). This will change the sequence and reset timing. If this has a positive impact or change, then we can inspect the timing more closely as a next step. Let me know if this makes sense. Thanks, Jasonhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1647985/dlp9000-inquiry-regarding-the-time-required-for-transitions-by-trigger-hz-for-dlp9000-single-dual-quad-and-global-reset-modes/6386444Wed, 17 Jun 2026 17:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c31a935f-6c7a-4547-9788-338d77b06bb8Tristan BottoneJH Sin, The timing between an FPGA trigger and the point at which a new image is fully displayed on the DMD depends on several factors within the DLPC910 and DLP9000 system, including the selected reset mode, pattern configuration, controller sequencing, mirror reset behavior, and the overall operating conditions. One important clarification is that the DLPC910 itself does not have a dedicated external trigger input pin. In a typical implementation, the trigger is handled by the Applications FPGA, which controls the DLPC910 through the DVALID, BLKMD, BLKAD, and RST2BLKZ signals. The FPGA effectively serves as the controller layer, while the DLPC910 provides status information back through the RST_ACTIVE signal, which is the primary timing reference for determining when a mirror update is in progress. The path from a trigger event to a stable image on the DMD consists of three distinct phases: data loading, mirror updating, and mirror settling. During the data-loading phase, the FPGA asserts DVALID together with the appropriate block-control signals, allowing pixel data to be transferred into the DMD SRAM through the LVDS interfaces. At a 480 MHz DDC_DCLK rate, each block requires approximately 4.167 &#181;s to load 100 rows, or roughly 1,480 MCP clock cycles. Importantly, this operation only updates the SRAM contents; the mirrors remain in their previous state until a Mirror Clocking Pulse (MCP) is issued. Once the desired data has been loaded, the FPGA initiates the mirror update by asserting BLKMD and BLKAD. In response, the DLPC910 drives RST_ACTIVE HIGH within approximately 60 ns and maintains this state for roughly 4 &#181;s while the mirror reset operation is performed. When RST_ACTIVE returns LOW, the mirrors have completed their reset sequence but still require additional settling time before the displayed image can be considered stable. Following the reset operation, the mirrors typically require an additional ~6 &#181;s to settle into their final landed positions. Illumination should not be enabled until this settling interval has elapsed. These timing values (~4.167 &#181;s per block load, ~4 &#181;s of RST_ACTIVE duration, and ~6 &#181;s of mirror-settling time) are fixed hardware characteristics defined in Section 7.4.4 and Table 7-13 of the DLPC910 datasheet . Since there is no separate “image ready” output, the recommended approach is to monitor RST_ACTIVE, wait for it to deassert, allow the settling interval to expire, and then enable illumination. For a Global Reset configuration using an external trigger, the most practical approach is often to preload all sixteen blocks into DMD SRAM prior to the trigger event. In this case, the trigger can immediately initiate the global MCP sequence, eliminating the SRAM loading delay from the trigger-to-display path. Under these conditions, the trigger-to-display latency is primarily associated with the mirror update and settling process, rather than SRAM loading time. The exact latency will depend on the operating configuration and timing implementation. Figure 7-11 of the DLPC910 datasheet provides an example of this timing relationship for the Global Reset operating mode. With respect to trigger frequency, the timing associated with data loading, RST_ACTIVE duration, and mirror settling is determined by the DDC_DCLK frequency and DMD hardware operation, not by the trigger rate itself. As a result, these timing components remain essentially unchanged whether the system is operating at 10 kHz or 15 kHz. What changes is the amount of exposure time remaining within each frame period after these fixed timing overheads have been accounted for. At 15 kHz, the frame period is approximately 66.7 &#181;s, whereas at 10 kHz it is 100 &#181;s, leaving a larger exposure window available at the lower trigger frequency. For additional timing details showing the relationship between DVALID, BLK_MD/BLK_AD, RST_ACTIVE, mirror settling, and exposure timing, please refer to Figures 7-8 through 7-11 of the DLPC910 datasheet (DLPS064D) , which provide timing diagrams for the Single, Dual, Quad, and Global reset modes. ** All of this information above can be found in the DLPC910 Datasheet. Datasheet is linked here -&gt; DLPC910 Datasheet ** The DLPLCRC910EVM and DLPLCRC910EVM Apps FPGA User Guide&#39;s are also extremely beneficial to review. Both are linked below. The user guides also have helpful information regarding external trigger and the utilization of triggers in the system design. DLPLCRC910EVM User Guide DLPLCRC910EVM Apps FPGA Users Guide Best Regards, Tristan Bottonehttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1656273/dlp2010nir-mems-plmWed, 17 Jun 2026 14:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cd3ccf1b-4026-4143-8e0e-76ff620474a9Domitille SchannePart Number: DLP2010NIR Hello, I am interested in the new MEMS PLM from TI in the NIR range. Where can I purchase it with the dedicated driver or evaluation board ? Thank you in advance,DLP2010NIRhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6386017Wed, 17 Jun 2026 12:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:adcea020-2e02-4f7a-8210-859f230f42d4zhihao dengAPI refers to DLP api → DLPC_API → samples → DLPC347x_dual_sampleshttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6385798Wed, 17 Jun 2026 09:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:60e66ce5-efd9-45f0-87f7-0ec2242d79d2zhihao dengDear Aaron, Thank you very much for replying to my question so promptly. TI is really efficient. Yes, the circuit diagram we designed can be said to be almost the same as the TI_EVM circuit board you shared in the part of DLPA3005 + DLPC3479_dual + DLP4710LC. We just modified the circuit of the USB-to-IIC part to make the FPGA directly output the IIC signal. The IIC signal output by the FPGA can realize the output of images such as checkerboards and stripe patterns in the external mode. So I think there should be no problem with the written IIC driver. The system is initialized normally, and IRQ_HOST_Master and IRQ_HOST_Slave operate normally as required by the data manual. So I have the following questions: 1. Does the ability to run the external mode prove that there is no problem with the hardware circuit? 2. The FLASH chip used is W25Q64JVSSIQ. There shouldn&#39;t be a problem with the use of the FLASH chip, right? 3. Is there a delay requirement between the relevant commands for starting the internal pattern stream? Is the following write command I used correct: (1) 98 01 02 01 04 00 00 00 00 00 00 00 00 A0 0F 00 00 20 03 00 00 1E 000 0 00 The is purpose to load pattern2 because there is only one picture in it. (2) 9E 01 00 (Stop) (3) 92 00 00 00 00 00 + 92 01 00 00 00 00 (Disable trigger) (4) 90 00 (Free run) (5) 94 00 (Do not enable image ready) (6) 05 04 (Enable internal mode) (7) 500ms delay (8) 9E 00 FF (Infinite loop) I found that the 98h command requires 25B in the &quot;DLPC3479 Software Programming Guide&quot;, but actually only 24B is used in the API. When I use 98h 02 + 24 zeros, an IIC communication error will occur, while using 98h 02 + 23 zeros won&#39;t. The following are the relevant pictures of the system. They are schematic diagrams 1, 2, and 3 respectively, and abnormal picture 4 (abnormalities occur always, not occasionally).Figure 5 shows the checkerboard in the external mode. Where should I start troubleshooting the problem now? Could you please give me some guidance? Thank you! Best, zhihaohttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654838/dmd-diffraction-efficiency-calculator-access-to-the-diffraction-efficiency-calculator/6385779Wed, 17 Jun 2026 09:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:be42f238-ad24-4b55-898a-9fdb04b41b5bJulia LangensteinHello Aaron, Why is the diffraction efficiency only at twice the mirror tilt angle at a maximum? And not for every angle which fulfills the blazing condition? Best regards, Juliahttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1651808/dlp3021-q1-follow-up-on-fpga-initialization-issue-on-dlp3021-q1-vs-dlp2021-q1/6385674Wed, 17 Jun 2026 07:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f2e9584-7c0d-4648-b69c-2b862f7be8b3Johns ChuangHi Jason, Thanks for the follow-up. Here is the feedback from our latest tests on the failing unit: 1. Power-up Sequence: We’ve corrected the sequence to align with Xilinx&#39;s recommendation, but the issue persists. 2. BROWN_OUT Reset: We added a routine to toggle BROWN_OUT (low-to-high) right after power-up to clear any potential bad state, but this did not resolve the problem. 3. Sequence Abort Register Status: Normal: 26 (0x1A) Failed: 2 (0x02) 4. Is there support for 0x7C functionality within the DLP Control Program, or are there specific scripting commands available that we can use to trigger this? Looking forward to your insights. Best, Johnshttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654839/dlpa3005-dlpa3005-s-illum_bw_bcx-register/6385362Wed, 17 Jun 2026 03:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:11ed6ae2-6008-46f0-8120-ebbf1993afffTanabe MasakiHello. I am developing a DLP projector using DLPC3479, DLPA3005, and DLP4710. This time, we are contacting you to request support regarding the LED driver DLPA3005. Currently, the DLPA3005 is illuminating the following two types of LEDs: ① LEDs with one LED built into the LED package ② LEDs with two LEDs built into the LED package in series (Vf is approximately twice that of ①) The current waveforms when LEDs ① and ② are lit are shown below (100mV/A) In ①, the ringing subsides immediately after the peak of the inrush current, but in ②, the current appears to be still increasing to the predetermined value even after the initial peak has fallen. I think that the response of the LED driver&#39;s control loop is delayed in ② because the forward voltage is approximately twice that of ①. Therefore, upon re-examining the DLPA3005 datasheet, I found the following description on page 22. --------------------------------------------------------------------------------------------------------------------------------------- When, for instance, two LEDs in series are connected, or when a relatively high wiring resistance is present in the loop, the loop gain will reduce due to the extra attenuation caused by the increased series resistances of rLED + RWIRE +RON. As a result, the loop response time lowers. To compensate for this increased attenuation, the loop gain can be increased by selecting a higher gain for the programmable gain block. The gain increase can be set through register ILLUM_BW_BCx. Under normal circumstances the default gain setting (00h) is sufficient. In case of a series connection of two LEDs setting 01h or 02h might suffice. --------------------------------------------------------------------------------------------------------------------------------------- It appears that the loop gain of the control loop can be increased by changing the gain setting of the ILLUM_BW_BCx register shown here. I would like to check if changing this register setting improves the current waveform when the LED in ② is lit. I would like to access this register externally. Is there any way to do this? I would appreciate your guidance. Thank you.https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1655614/dlpc3479-the-internal-mode-display-of-dlp4710-dlpc3479_dual-is-abnormal/6385149Tue, 16 Jun 2026 22:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f74e82f3-cbed-459b-bb62-da460ed464c8Aaron BlackHello Zhihao, Have you followed this simplified schematic and made sure to connect the secondary ASIC to flash as well? I apologize, I can&#39;t do as well of a check here, but it seems like 1 controllers data is being lost: There was a bug fix for an issue during changing modes where the ASIC could drop out, but this was intermittently an issue not every time. It just seems like the Flash data is not actually being stored anywhere. Best, Aaronhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1654838/dmd-diffraction-efficiency-calculator-access-to-the-diffraction-efficiency-calculator/6385135Tue, 16 Jun 2026 22:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8a47119f-94c0-404f-9372-16d84de62f54Aaron BlackHello Julia, Depending on the device you are testing, the pixel tilt angle can be different, which makes the maximum efficiency twice the micromirror tilt - seen in the datasheet. The blazing condition is simply the max efficiency reflection angle of the mirror to produce diffraction orders. You can have multiple illumination angles that fulfill blaze conditions. This calculator can help find those conditions - you can sweep through many different angles in order to find the combination optical and micromirror tilt angles. Hope this helps! Best, Aaron