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DLPC410: DLPC410 CLKIN_R requirements?

Ohad
Prodigy 70 points
Part Number: DLPC410
Other Parts Discussed in Thread: DLPLCRC410EVM

Hello,

I design a board with the DLPC410 which controls DMD at data rate of 800Mbps.

My question is regarding the DLPC410 Ref Clock: "CLKIN_R".

According the datasheet -  "The reference clock, CLKIN_R, supplied from an oscillator must be 50 MHz".

However I couldn't find any constraints/requirements on the clock signal except of voltage levels of the LVCMOS2.5V, furthermore - in the EVB reference the clock is sourced by an FPGA I/O .

Can I use FPGA's I/O as a clock source with no concerns or should I use a dedicated oscillator ?

Thank you very much.

Ohad

  • 0
    TI__Mastermind 43135 points

    Hello Ohad,

    Good to hear from you again.  

    On the DLPLCRC410EVM (latest version of the EVM - design files here: DLPC410 Board Design Files (Rev. B)) there is an oscillator that feeds the APPS_FPGA (Xilinx Virtex5 LX50).  It is labeled U9 on page 6 of the schematic pdf.  This is used to drive the logic in the APPS_FPGA, but is also passed on to the DLPC410.

    On that same page it shows that CLKIN_R is output on pin AE18 from the APPS_FPGA to pin AD13 of the DLPC410 (on page 10).  So it passes the CLK_OSC_50M signal through to the DLPC410.

    There should be no reason you cannot feed it from an output of whatever FPGA or µ-processor you feed the DLPC410 from.  It should however meet or exceed the specifications of the oscillator that is used in the EVM (Abracon - ASVMPC-50.000MHZ-LR-T)  [i.e. rise/fall time, duty cycle, jitter, etc . . . ].

    Fizix

  • 0 in reply to Fizix
    Prodigy 70 points

    Hi Fizix,

    Thank you very much for your detailed response, I'll use the FPGA Output to source the clock.

    Best regards,

    Ohad