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Part Number: DLPC3430
Hi there—I have two questions with regard to the following statement in section 18.104.22.168 of the datasheet: "SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state while power is applied to the controller."
Kind regards,Jeff LaBundy
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Kindly find the answer to your questions below:1. Which DLPC3430 supplies must remain active to satisfy the requirement that "power is applied to the controller?" In our design, RESETZ is controlled by the companion DLPA3000, so we can only pull RESETZ low by pulling PROJ_ON of the DLPA3000 low, but this disables several supplies. However, we control VCC_FLSH separately and it remains powered while RESETZ = 0 and our host processor programs the SPI flash. Since VCC_FLSH represents the I/O supply for the DLPC3430 SPI pins, I'm assuming that powering VCC_FLSH is sufficient to satisfy the aforementioned requirement and prevents the host from back-powering any protection diodes in the DLPC3430. However if this assumption is incorrect, please let me know.
TI> Yes, you are correct. Supplying VCC_FLSH and pulling PROJ_ON low should be enough to get access to the SPI Flash lines.
2. What is the upper bound for the delay between PROJ_ON = 0/1 and RESETZ = 0/1? The datasheet suggests at least 30 ms plus some additional unspecified delay. Since we cannot control RESETZ directly, we need to know how long to wait after pulling PROJ_ON low before it is safe for our host processor to take its SPI master out of tri-state.
TI> As per Figure 18. Power Sequence Normal Shutdown Mode provided on the DLPA3000 datasheet, there is a total of 25+10 = 35ms between PROJ_ON going low and RESETZ assertion.
Thanks & Regards,
Thanks & Regards,Hirak.
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In reply to Hirak Biswas:
Hi Hirak—thank you for your prompt and thorough support.
Your response has answered my questions in full—thank you for helping me to find the timing I was looking for in Figure 18, and we'll leave VCC_FLSH active while PROJ_ON = 0 and our host programs the SPI flash.
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