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DLPC3478: Suspend/resume external pattern streaming mode

Part Number: DLPC3478

Hi,

we're using the DLP3478 in external pattern streaming mode.  The patterns are transferred to the DLPC from an FPGA.   We have a camera system to capture the projected patterns, synchronised by using the trigger out signals.  The projector is not continuously streaming, we would like to project a few images/patterns in bursts, and then stop the projector between captures.  Further, we run the pixel clock, PCLK, at constant frequency @148.5 MHz.

Questions:

1. Do we need to keep the VSYNC_WE running all the time, even between captures?

2. Does this also apply to the HSYNC_CS and DATAEN_CMD?

3. What is the recommended procedure for burst like operation as mentioned above?  Is there a way to suspend the projector, or should we transfer 0x0 to the DLPC between the captures?

4. If we want to change the frame rate we plan to only modify the horisontal blanking, at a frame boundry, of the parallel data format sent from the FPGA to the DLPC.  Would this be OK, what are the limitations regarding maximum horisontal blanking?

EDIT:

Here are two screenshots showing what we try to achieve.

The first image is from the first capture after we power up our system.

The next image shows the second capture, notice now that the dlpc_trig_2 signal asserts immediately when vsync goes high.

We would like to somehow reset the state of the DLPC such that a second capture behaves like the first capture above.

Thanks,

best regards,

Ronny

  • Hi Ronny,

    We are looking into your request. Get back to you in the next 24 hours.

    Regards,

    Sanjeev 

  • Hi Ronny,

    I am looking into your queries and will get back to you in a couple of days.

    Thanks for your patience in advance.

    Regards,

    Mayank

  • Ronny,

    Please refer to my responses as follows -

     1. Do we need to keep the VSYNC_WE running all the time, even between captures?

    >> Yes, otherwise the sequencer will stop causing the LEDs to be turned off.

    2. Does this also apply to the HSYNC_CS and DATAEN_CMD?

    >> It is expected that parallel interface requirement is met during the external pattern display and hence it is required that these signals also remain active.

    3. What is the recommended procedure for burst like operation as mentioned above?  Is there a way to suspend the projector, or should we transfer 0x0 to the DLPC between the captures?

    >> Are you trying to display 2D patterns and will the patterns be changing on the fly? If yes, then the external pattern mode is only mode suitable for this case. One way to suspend the projector is to change the operating mode to Standby. 

    4. If we want to change the frame rate we plan to only modify the horizontal blanking, at a frame boundary, of the parallel data format sent from the FPGA to the DLPC.  Would this be OK, what are the limitations regarding maximum horizontal blanking?

    >> As long as the parallel interface timing requirements are met as given in the datasheet, this should be ok.

    Please let me know if you have any further queries.

    Regards,

    Mayank

  • Hi Mayank,

    thank you for the answers.

    To follow up, please refer to the screenshots in the original post.  The first capture is OK, the second capture is not.  Notice in the second screenshot that the DLPC generates a trigger out signal during the first Vsync period. The projector has been in Standby operating mode between the captures.  Shouldn't the 2 captures behave the same since we put the projector in standby mode between captures?

    Regards,

    Ronny

  • Ronny,

    Does every subsequent capture after the first capture (e.g. 2,3,4,5) look like that of the second capture?

    Regards,

    Philippe Dollo

  • Hi, that is correct.

    Regards,

    Ronny

  • Ronny,

    Will it be possible for you to capture Trigger_out1 signal as well along with the other signals. It will help me debug this further.

    Thanks and regards,

    Mayank

  • Hi Mayank,

    sorry for the wait.  We actually don't use the trigger_out1 signal, so it hasn't been enabled (and is therefore constant low).

    Regards,

    Ronny

  • Ronny,

    I am currently looking into your query and will get back to you in a couple of days time.

    Regards,

    Mayank

  • Hi Ronny,

    Apologies for the delay in getting back.

    I tried reproducing the issue at my end but didn't see any misbehavior.

    Can you please share a screenshot of the external pattern display settings? 

    I assume you are configuring the trigger out 2 signal with some delay. Can you read back this delay value using "Read Trigger Out Configuration" during the second run?

    Regards,

    Mayank