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  • TI Thinks Resolved

DLPC6421: Keystone fail

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Replies: 15

Views: 217

Part Number: DLPC6421

I met a problem in my project dual DLPC6421 + FPGA + DLP470TP.

The image working fine with 4K/60Hz video input source.

When I enable the keystone function and setup the angle, the image become abnormal with many extra horizonal lines.

It can be recovered when the keystone angle go back to zero.

It would be appreciated if anyone can give me some hint to fix it.

Thank you.

  • Geoffrey,

    Welcome to the E2E forums, and thanks for your interest in our DLP technology.

    What keystone settings are you running at? What video source are you testing the keystone with? If you can share screenshots of the image abnormality, that would be helpful as well.

    Thanks and regards,

    Philippe Dollo

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  • In reply to Philippe Dollo:

    Hi Philippe,

    Thanks for your reply.

    The Video source is HDMI,

    FPGA FW version is 384.

    Keystone setting as follow:

    When the Pitch Angle setting is zero, the image as follow:

    When the pitch angle is non-zero, the image is as follow:

    It looks like the frame buffer has some problem, I guess.

    Geoffrey

  • In reply to Geoffrey Tseng1:

  • In reply to Geoffrey Tseng1:

    Geoffrey,

    Agreed. This looks like some kind of frame buffer or video interface issue. You may have something wrong in your board.

    I am looping in experts on this chipset to give more advice for this issue. Thanks for your patience.

    Regards,
    Philippe Dollo

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    If a post answers your question, please click the "Verify Answer" button.

    Have questions about DLP Pico Chipsets? Check out the DLP Pico Universal FAQ for quick answers: https://e2e.ti.com/support/dlp/f/94/t/946506 

  • In reply to Philippe Dollo:

    Hi Philippe,

    I send the keystone commands , 0 and 10 degree, and find the error log from DLPC6421 UART.

    => 0 degree:

    Write Cmd:FPGA_1DKeyAngle, addr:34, subAddr:f4 00 00 33 01 00 01 01 00 Write(OK)

     

    => UART message return:

    cmdF_SetKeystoneAngles pitch = 0, AnchorStep = 1

    dispfmt: dispfmt_FPGA_Keystone1DFrmFlash() - Couldn't matching Offset and/or Throw-Ratio

    dispfmt_FPGA_Keystone1D Pitch = 0 Throw_Ratio = 307 V_Offset = 256 DMD_Width = 1920, DMD_Height = 1080 Anchor_Step = 1

     

    => 10 degree:

    Write Cmd:FPGA_1DKeyAngle, addr:34, subAddr:f4 00 0a 33 01 00 01 01 00 Write(OK)

     

    => UART message return:

     cmdF_SetKeystoneAngles pitch = 2560, AnchorStep = 1

    dispfmt: dispfmt_FPGA_Keystone1DFrmFlash() - Couldn't matching Offset and/or Throw-Ratio

    dispfmt_FPGA_Keystone1D Pitch = 2560 Throw_Ratio = 307 V_Offset = 256 DMD_Width = 1920, DMD_Height = 1080 Anchor_Step = 1

    No matter what angle , the log always show error message - - Couldn't matching Offset and/or Throw-Ratio.

    Maybe it is a key for this issue.

    Geoffrey

  • In reply to Geoffrey Tseng1:

    Geoffrey,

    Can you please provide the DLPC6421 f/w version number and the FPGA version number?

    Are you working with local TI contacts? Do you have a DLPC6421 reference project? can you share it? 

    Please note this part is not a Mass Market part so it will be difficult to debug without looking at the version number and reference project.

    You can do one simple step - Goto composer project and [Flash Builder] tool then in the right side bottom there is an entry call Keystone.bin file - you can just remove it by changing Block Type column [Other Binary 1] to [Remove this block] now try the new image. It should work.

    Basically, the Keystone.bin file in the project is not in sync with the optical engine Offset and throw-ratio. settings, you need to re-generate the keystone.bin file with your optical engine settings and use in project.

    Benifit of having keystone.bin - faster execution of the function, not having - little bit slower...

    Regards,

    Sanjeev

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  • In reply to Sanjeev:

    Hi Sanjeev,

    I find one difference for ISSI DDR3.

    The reference design is IS43TR16640A-125JBLI.

    But I use IS43TR16640CL-125JBLI in my project.

    Is it possible to cause this kind of failure?

    FPGA FW version : 0.0.384

    DLPC6421 FW version : unknown , maybe 1.0

    May I have your e-mail to send you further data?

    Geoffrey

  • In reply to Geoffrey Tseng1:

    Geoffrey,

    Thanks for your feedback. The team should get back to you within next few days.

    Regards,

    Philippe

    --------------------------------------------------------------------------------------------------------

    If a post answers your question, please click the "Verify Answer" button.

    Have questions about DLP Pico Chipsets? Check out the DLP Pico Universal FAQ for quick answers: https://e2e.ti.com/support/dlp/f/94/t/946506 

  • In reply to Philippe Dollo:

    Geoffrey,

    Couple of things here -

    1. Please send me the DLPC6421 version info. This will help us look into the firmware -

    From the UART log -

    cmdF_SetKeystoneAngles pitch = 2560, AnchorStep = 1

    dispfmt: dispfmt_FPGA_Keystone1DFrmFlash() - Couldn't matching Offset and/or Throw-Ratio  => This error is clearly due to Keystone.bin not valid for the optical engine Vertical Offset and Throw Ratio. However in this situation. The firmware fall back to another method of computation i.e., the below line 

    dispfmt_FPGA_Keystone1D Pitch = 2560 Throw_Ratio = 307 V_Offset = 256 DMD_Width = 1920, DMD_Height = 1080 Anchor_Step = 1

    Now, we can safely ignore these errors because it only impact the command execution time. But if should Not cause the problem you are seeing.

    2. Yes, i see there can be a problem with FPGA DDR3 memory part. How did you make this selection, I suggest you relook at this part. The FPGA during power-up perform the memory BIST and there are commands to read the status. But this requires access to projector control software. Do you have access to those? If you can help us how you are working on this project, it will be helpful to assist you further - are you working with any DLP OEM, Third party design house? How did you get the DLPC6421 firmware image file and FPGA binary file?

     

    Regards,

    Sanjeev 

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  • In reply to Sanjeev:

    Hi Sanjeev,

    The FW version as follows: (from UART log)

    In Bootloader: v8.1

    Debug opened on URT0
    Fetching data from EEPROM device 3344 bytes
    EEPROM content is valid
    EEPROM: Initializing Slave EEPROM: 3344 bytes
    sysmon: System Startup State From PROJ_ON is 0
    sysmon: Notify uC ASIC is running.
    PAD Rev ID = 3
    sysmon: Low-power mode change cc = 1
    sysmon: Memory test cc = 1
    sysmon: System mailbox ID = f7ffa078
    API version: 02.00.b1
    App version: 02.00.b1
    ASIC ID: 50
    ASIC Configuration: 6421
    Configuration layout versions:
    Seq Map: 64.21.0002
    SW Map: 64.21.0001
    EEPROM: 01.04.0001

    And FPGA FW version is 0.0.384.

    Geoffrey

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