DLPC3436: LVDS Interface on FPGA

Josh5566

Prodigy 160 points

Part Number: DLPC3436

The FPGA needs two LVDS to connect DLPC3460 then output Sub-LVDS signal to DMD.

1. The each channel of LVDS is in front of FPGA how many is the frequency to need?

2. How many is the Sub-LVDS output frequency?

over 3 years ago

0 Philippe Dollo over 3 years ago

TI__Mastermind 28005 points

Josh,

Welcome to the E2E forums and thanks for your interest in our DLP technology.

The high speed DMD clock frequency on the output (right side) is rated at 600 MHz per the DLPC3436 datasheet (see section 6.16).

Meanwhile, the FPGA's input timings are designed to match that of the DLPC3436 (which has a maximum pixel clock of 155 MHz). Max supported resolution is 1920x1080 at 60 Hz.

I hope this helps.
Regards,

Philippe Dollo

0 Josh5566 over 3 years ago in reply to Philippe Dollo

Prodigy 160 points

Thanks Philippe

DLP®︎ products

DLP products forum

DLPC3436: LVDS Interface on FPGA