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Pre-installed programs

smith kevin
Prodigy 100 points

Other Parts Discussed in Thread: DLP7000, DLPC410

Hi, there

 I purchased a DLP4100 kit , and I want to know how can I get the Pre-installed programs in the FPGA. 

 Does it in the  supporting  codes ?

Thanks.

kevin

  • 0
    TI__Guru 54725 points

    Hello Kevin,

    There are two APPS_FPGA example programs:

    1. Pattern Generator- this code loads from the PROM when the board is powered up and cycles through 8 patterns continuously.
    2. Explorere GUI - This code is loaded when the kit is connected to a computer that has the D4100 drivers installed.

    Both source codes are available on the DLP Extranet for Catalog customers.  You must request access through the Design House that you purchased your kit from.  They take care of screening for compliance with US import/export laws.

  • 0 in reply to Fizix
    Prodigy 100 points

     Thank you very much for the quick reply.

    I find  there is some sample codes in the  gui_source_files  folder.     It   shows  some  errors  when  I   synthesize  a  project  contained  these codes by   ISE. How can I  utilize  these  codes ?

    Respectfully

    kevin

  • 0 in reply to smith kevin
    TI__Guru 54725 points

    Kevin,

    Can you tell me what kind of errors.  I will tell you that some of the build depends on some standard libraries that you must dowload from Xilinx.  For example one of the builds requires their DDR memory block.  This is analogous to standard libraries in C++.  Generally the project code does not include them in the source.

    Please check the error log to see if there are libraries it is expecting to see.

    Fizix 

  • 0 in reply to Fizix
    Prodigy 100 points

    1.In  the line 34  of   "appscore_e.vhd “ file  , library  DDR2  cannot  be  found

    2.In  the line 35  of   ”appscore_e.vhd“  file ,  library  DDR2   is   not  declared.

    I think  you are right  that I should  download  the DDR2  library .But   I  cannot  find it  in  xilnx 's offical  website, can  you provide  it  to  me?

  • 0 in reply to smith kevin
    TI__Guru 54725 points

    Kevin,

    You need the MIG (Memory Interface Generator) Tool which is part of the ISE Design Suite.  Try starting at this page --> http://www.xilinx.com/products/intellectual-property/MIG.htm.  I think you will need to download the ISE Design Suite which includes the MIG.  I believe you will have to create a Xilinx login before you can download anything.

    Fizix.

  • 0 in reply to Fizix
    Prodigy 100 points

    Fizix,

    Thank you for your  reply.

    The design tool  I  used  is   ISE13.3  ,which   contained    MIG 3.61   .So   I  think  it  is not the problem  of  MIG  .

    I  also  want  to know   if  there  are  some steps  should be  taken  to ensure the  project   ,which  contained   those  sample  codes in the  gui_source_files  folder,  run  correctly.

    Regards,

    kevin

  • 0 in reply to smith kevin
    TI__Guru 54725 points

    Kevin,

    My understanding is that you use the MIG tool Wizard to select the Xilinx chip type you are working with and the memory type you are using.  The tool then generates the DDR2 core.  You can the view and edit the HDL files.  See the following link:  --> http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/DDR2-memory-controller-IP-free-with-purchase-of-development/td-p/52973

    I understand from reading the linked thread that DDR2 memory can be challenging.

    Fizix

  • 0 in reply to smith kevin
    Prodigy 30 points

    Hi Kevin,

    I am also getting same error message. Have fixed this issue, if yes please let me know the path to download DDR2 library.

    Thanks in advance !

  • 0 in reply to Hariharan Padmanabhan
    TI__Guru 54725 points

    Hariaharan,

    Please contact the Design House that you purchased the kit from and request an updated copy of the APPS_FPGA GUI project. 

    Fizix

  • 0 in reply to Fizix
    Prodigy 30 points

    Hi Fizix,

    Thanks for your immediate reply.

    I have another doubt, please help me on this.

    I am trying to control DMD (Digital micromirror devices DLP4100 768x1028) using FPGA virtex 5. I have 32 input lines (Port A 16 and Port B 16) using which I am trying to control first 32 columns of first row.

    Could you please give me some sample HDL program for this.

    Thanks in advance !

    DMD DLP4100

    Virtex 5 XC5VLX50-1FF1153

  • 0 in reply to Hariharan Padmanabhan
    TI__Guru 54725 points

    Hi Hariaharan,

    We have the Design Houses provide the HDL sample code for this to ensure compliance with Unites States Export regulations.  Please make this request to the Design House that you purchased the kit from.  They should be able to supply what you are asking for. 

    I also think there may be some misunderstaning of the DLP7000 (XGA DMD) with the DLPC410.  You must always load an entire row into the device, even if you load all zeros into the remaining columns of a particular row.  Please refer to the DLP7000, DLPC410 Datasheet and the Discovery 4100 Chipset Document:

    http://www.ti.com/lit/gpn/dlp7000

    http://www.ti.com/lit/gpn/dlpc410

    http://www.ti.com/litv/pdf/dlpu008a

    Fizix