DLPA2000: PG failure

Wladimir,

What DMD do you have connected to the DLPC3433? You must have a DMD for the system to boot. On a similar note, did you get your firmware from the DLP Pico Firmware Selector Tool? If so, which build did you download?

For starters, you may want to verify the startup signals against the DLPC3433 datasheet's boot-up timing diagram. https://www.ti.com/lit/gpn/DLPC3433 

Regards,

Philippe Dollo

Update: My board is feeding with 1.8 LS_IN. When PROJ_ON is pulled high, there is a small drop in LS_IN to 1.7V. Is this minimum limit that sensitive? Could it be a reason for failure?

Philipe,

There is a DMD from a third-party based on the DLP3010. I had DMD connected and the DLPC3433 did not boot up (IRQ always high). And now debugging I find that LS_OUT is not giving 1.8V. The firmware was provided by the displays vendor and I have tested it sucessfully on the reference design. I also verified the boot up sequence on the DLPC3433. But as expected since VCC18 is under the accepted minimum the boot up sequence is interrupted. So, I guess the DLPA2000 is stuck because the LS_OUT voltage is 1.3v

Wladimir,

Did you see this thread from a different customer with a similar issue?

https://e2e.ti.com/support/dlp/f/dlp-products-forum/928554/dlpa2005-when-proj_on-is-pulled-low-1v8-on-ls_out-falls-to-just-0-946v

What behavior are you seeing on PCLK?

Regards,

Philippe

Hi Philippe,

Maybe I have found a serious error on our board. It turns out that PCLK, and the other signals for parallel input control PDM, Vsync, Hsync, and Data_enCMD are left floating. I do not need parallel input, but DSI. Is it very critical that these pins are not grounded via a resistor?. Maybe is there any possible workaround, or another way to verify/change the state of PCLK?

Thanks