CCS/TMS320C5545: How can I program in ROM?

How can I save the code data?

I want to program the code in flash

Hi

Actually, I have an I2C EEPROM.

I want to program the code in the I2C EEPROM

and I found example code "programmer" (c55_lp/c55_csl3.08/ccs_v6.x_examples)

* This utility allows a user-specified binary file to be programmed into
* one of the following supported devices...
* @li NAND FLASH
* @li NOR FLASH
* @li SPI EEPROM
* @li IIC EEPROM
* @li MMC
* @li SD
* @li SPI Flash
* @li MCSPI Flash

I made Hex file from hex utility.

But I don't know how to make binary file.

Can I make a binary file for code?

Thank you

Hi minkyo seo,

The hex55 program does generate the binary file - you have named it .hex.

Use these parameter flags with hex55: hex55 -boot -v5505 -serial8 -b -i Bootloader.out -o Bootloader.bin

I find it helpful to put the command with flags inside of a .bat file that I execute.

Then to flash the I2C EEPROM, use c55_csl\ccs_v6.x_examples\programmer project. (http://www.ti.com/tool/sprc133)

When running the programmer, there will be a prompt in the CCS console. Type 4 for IIC EEPROM, 1 to program, and then pass the path to the .bin file generated by hex55. Note that there must not be any white spaces in the path, so move it somewhere like c:\ti\bins before programming.

What I2C EEPROM are you trying to program? We can confirm that the I2C address matches that which is used by the programmer (0x50).

Hope this helps,
Mark

Hi

I did it. but it is not working.

This is my setting.

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and I changed file name hex to bin. and this is build result

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Next I executed programmer example. this is result.

I think Programming complete is it is done. But DSP is not working. 

What is my mistake? 

I'm using AT24C512C  I2C EEPROM. 

Thank you 

Hi Mark.

I have some problem.

Could you help me?

Actually I programed in I2C eeprom.

But it is not working well.

When I program in Ram, it's working well.

But in I2C eeprom, it is not working DMA. i'm not sure that I2S is working as well.

I think it is initialization problem you said above.

I read some datasheet and I made initialization for PLL and Port and reset peripherals.

this is my code . please check for me

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#include "csl_dma.h"

#include "csl_i2s.h"

#include <csl_general.h>

#include <stdio.h>

#include "csl_sysctrl.h"

#include "csl_intc.h"

#include "DAC_PCM5142.h"

#include "csl_pll.h"

#include "csl_general.h"

#include "csl_pllAux.h"

#define CSL_TEST_FAILED         (1)

#define CSL_TEST_PASSED         (0)

#define CSL_DMA0_CH0            (0)

#define CSL_I2S_DMA_BUF_LEN (88)

#define DMA_DATA_LENGTH         CSL_I2S_DMA_BUF_LEN*4;

CSL_DMA_ChannelObj dmaObj0,dmaObj1,dmaObj2,dmaObj3;

CSL_DMA_Handle dmaLeftTxHandle;

CSL_DMA_Handle dmaRightTxHandle;

CSL_DMA_Handle dmaLeftRxHandle;

CSL_DMA_Handle dmaRightRxHandle;

CSL_DMA_Config dmaConfig;

CSL_I2sHandle   hI2s, hI2s_2;

CSL_IRQ_Dispatch     dispatchTable;

PLL_Obj pllObj;

PLL_Config pllCfg1;

PLL_Handle hPll;

PLL_Config *pConfigInfo;

PLL_Config pllCfg_12p288MHz = {0x8173, 0x8000, 0x0806, 0x0000};

PLL_Config pllCfg_40MHz     = {0x8988, 0x8000, 0x0806, 0x0201};

PLL_Config pllCfg_60MHz     = {0x8724, 0x8000, 0x0806, 0x0000};

PLL_Config pllCfg_75MHz     = {0x88ED, 0x8000, 0x0806, 0x0000};

PLL_Config pllCfg_100MHz    = {0x8BE8, 0x8000, 0x0806, 0x0000};

PLL_Config pllCfg_120MHz    = {0x8E4A, 0x8000, 0x0806, 0x0000};

volatile Uint16 dmaTxFrameCount = 0, dmaRxFrameCount=0, dmaIntCount,toggle;

#pragma DATA_ALIGN(i2sDmaWriteLeftBuff, 32);

Uint32 i2sDmaWriteLeftBuff[CSL_I2S_DMA_BUF_LEN];

#pragma DATA_ALIGN(i2sDmaWriteRightBuff, 32);

Uint32 i2sDmaWriteRightBuff[CSL_I2S_DMA_BUF_LEN];

#pragma DATA_ALIGN(i2sDmaReadLeftBuff, 32);

Uint32 i2sDmaReadLeftBuff[CSL_I2S_DMA_BUF_LEN];

#pragma DATA_ALIGN(i2sDmaReadRightBuff, 32);

Uint32 i2sDmaReadRightBuff[CSL_I2S_DMA_BUF_LEN];

interrupt void DmaIsr(void);

void UserAlgorithm(void);

void pll_sample()

{

    CSL_Status status;

   PLL_init(&pllObj, CSL_PLL_INST_0);

    hPll = (PLL_Handle)(&pllObj);

    PLL_reset(hPll);

   /* Configure the PLL for 100MHz */

   pConfigInfo = &pllCfg_100MHz;

  PLL_config (hPll, pConfigInfo);

//PLL configuration complete

//The below code is for demonstrating additional CSL PLL APIs

    PLL_getConfig(hPll, &pllCfg1); //demonstrates geting the PLL configuration

   PLL_bypass(hPll); //demonstrates the PLL bypass and power down

   PLL_enable(hPll); //demonstrates PLL power up & enabling with the previous configuration

/////////////////////////////////////////////////////////////////////////

}

void I2S_set(void)

{

I2S_Config hwConfig;

////////////////////////////////////////////////////////////////////////////////////////////////////  I2S_0

hI2s = I2S_open(I2S_INSTANCE0, DMA_POLLED, I2S_CHAN_STEREO);

SYS_setEBSR(CSL_EBSR_FIELD_SP0MODE, CSL_EBSR_SP0MODE_1);  // i2s0 port set

/** Set the value for the configure structure */

hwConfig.dataType = I2S_STEREO_ENABLE;            // 0 stereo  1mono

//hwConfig.loopBackMode = I2S_LOOPBACK_ENABLE;          // 1 enable 0disable

hwConfig.loopBackMode       = I2S_LOOPBACK_DISABLE;          // 1 enable 0disable

hwConfig.fsPol = I2S_FSPOL_LOW;                // ws low = left ch

hwConfig.clkPol = I2S_FALLING_EDGE;             //Receive data is sampled on the falling edge and transmit data shifted on

                                                            // the rising edge of the bit clock.

hwConfig.datadelay = I2S_DATADELAY_ONEBIT;        //0 -> 1bit delay 1-> 2bit delay

hwConfig.datapack = I2S_DATAPACK_DISABLE;        //

hwConfig.signext = I2S_SIGNEXT_DISABLE;        //extension of words

hwConfig.wordLen = I2S_WORDLEN_16;             // 0-8, 1-10, 2-12, 3-14, 4-16, 5-18, 6-20, 7-22,8-24

//hwConfig.i2sMode = I2S_MASTER;                 // 0-slave, 1-master

hwConfig.i2sMode            = I2S_SLAVE;                 // 0-slave, 1-master

hwConfig.FError = I2S_FSERROR_DISABLE;

hwConfig.OuError = I2S_OUERROR_DISABLE;

I2S_setup(hI2s, &hwConfig);

///////////////////////////////////////////////////////////////////////////////////////////////  I2S_2

hI2s_2 = I2S_open(I2S_INSTANCE2, DMA_POLLED, I2S_CHAN_STEREO);

    SYS_setEBSR(CSL_EBSR_FIELD_PPMODE, CSL_EBSR_PPMODE_6);    //  i2s2 mode setup

    /** Set the value for the configure structure               */

    hwConfig.dataType           = I2S_STEREO_ENABLE;            // 0 stereo  1mono

    //hwConfig.loopBackMode         = I2S_LOOPBACK_ENABLE;          // 1 enable 0disable

    hwConfig.loopBackMode       = I2S_LOOPBACK_DISABLE;          // 1 enable 0disable

    hwConfig.fsPol              = I2S_FSPOL_LOW;                //

    hwConfig.clkPol             = I2S_FALLING_EDGE;             //Receive data is sampled on the falling edge and transmit data shifted on

                                                                // the rising edge of the bit clock.

    hwConfig.datadelay          = I2S_DATADELAY_ONEBIT;        //0 -> 1bit delay 1-> 2bit delay

    hwConfig.datapack           = I2S_DATAPACK_DISABLE;        //

    hwConfig.signext            = I2S_SIGNEXT_DISABLE;        //extension of words

    hwConfig.wordLen            = I2S_WORDLEN_16;             // 0-8, 1-10, 2-12, 3-14, 4-16, 5-18, 6-20, 7-22,8-24

//    hwConfig.i2sMode            = I2S_MASTER;                 // 0-slave, 1-master

    hwConfig.i2sMode            = I2S_SLAVE;                 // 0-slave, 1-master

    //hwConfig.clkDiv             = I2S_CLKDIV8;                //I2Sn_CLK = SystemClock / (2CLKDIV+1)

    //hwConfig.fsDiv              = I2S_FSDIV256;                //I2Sn_FS = I2Sn_CLK / (2FSDIV+3)

    hwConfig.FError             = I2S_FSERROR_DISABLE;

    hwConfig.OuError            = I2S_OUERROR_DISABLE;

    I2S_setup(hI2s_2, &hwConfig);

}

void DMA_set(void)

{

    Int16           status = CSL_TEST_FAILED, ifrValue;

    IRQ_disable(DMA_EVENT);

    IRQ_clear(DMA_EVENT);

    CSL_SYSCTRL_REGS->DMAIER = 0x0000;

    ifrValue = CSL_SYSCTRL_REGS->DMAIFR;

    CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;

    IRQ_plug(DMA_EVENT, &DmaIsr); // dma interrupt set

DMA_init();  //dma clock enable

    IRQ_enable(DMA_EVENT); // dma interrupt enable

////////////////////////////////////////////////////////////// I2S0_RX_Left Channel DMA ch1

dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;

dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;

dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;

dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;

dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S0_RX;

dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;

dmaConfig.chanDir      = CSL_DMA_READ;

dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;

dmaConfig.dataLen      = DMA_DATA_LENGTH;

dmaConfig.srcAddr      = (Uint32)&CSL_I2S0_REGS->I2SRXLT0;// I2S0_I2SRXLT0

dmaConfig.destAddr     = (Uint32)i2sDmaReadLeftBuff;

dmaLeftRxHandle = DMA_open(CSL_DMA_CHAN1, &dmaObj0,&status);

    DMA_config(dmaLeftRxHandle, &dmaConfig);

////////////////////////////////////////////////////////////////// I2S0_RX_Right Channel DMA ch2

dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;

dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;

dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;

dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;

dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S0_RX;

dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;

dmaConfig.chanDir      = CSL_DMA_READ;

dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;

dmaConfig.dataLen      = DMA_DATA_LENGTH;

dmaConfig.srcAddr      = (Uint32)&CSL_I2S0_REGS->I2SRXRT0; //I2S0_I2SRXRT0

dmaConfig.destAddr     = (Uint32)i2sDmaReadRightBuff;

dmaRightRxHandle = DMA_open(CSL_DMA_CHAN2, &dmaObj1,&status);

    DMA_config(dmaRightRxHandle, &dmaConfig);

////////////////////////////////////////////////////////////////// I2S2_TX_LEFT Channel DMA ch4

    dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;

    dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;

    dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;

    dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;

    dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_TX;

    dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;

    dmaConfig.chanDir      = CSL_DMA_WRITE;

    dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;

    dmaConfig.dataLen      = DMA_DATA_LENGTH;

    dmaConfig.srcAddr      = (Uint32)i2sDmaWriteLeftBuff;

//    dmaConfig.srcAddr      = (Uint32)i2sDmaReadLeftBuff;

    dmaConfig.destAddr     = (Uint32)(0x2A08);

    dmaLeftTxHandle = DMA_open(CSL_DMA_CHAN4, &dmaObj2,&status);

    DMA_config(dmaLeftTxHandle, &dmaConfig);

    ////////////////////////////////////////////////////////////////// I2S2_TX_Right Channel DMA ch5

    dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;

    dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;

    dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;

    dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;

    dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_TX;

    dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;

    dmaConfig.chanDir      = CSL_DMA_WRITE;

    dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;

    dmaConfig.dataLen      = DMA_DATA_LENGTH;

    dmaConfig.srcAddr      = (Uint32)i2sDmaWriteRightBuff;

//    dmaConfig.srcAddr      = (Uint32)i2sDmaReadRightBuff;

    dmaConfig.destAddr     = (Uint32)(0x2A0C);

    dmaRightTxHandle = DMA_open(CSL_DMA_CHAN5, &dmaObj3,&status);

    DMA_config(dmaRightTxHandle, &dmaConfig);

}

interrupt void DmaIsr(void)

{

    volatile Uint16 ifrValue;

    ifrValue = CSL_SYSCTRL_REGS->DMAIFR;

    CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;

    if (ifrValue & 4)                 // DMA ch 4,5 Tx

    {

        dmaTxFrameCount++;

    }

    if (ifrValue & 5)

    {

        dmaTxFrameCount++;

    }

    if (ifrValue & 1)               // DMA ch 1,2 Rx

    {

        dmaRxFrameCount++;

    }

    if (ifrValue & 2)

    {

        dmaRxFrameCount++;

    }

    dmaIntCount++;

}

void waitloop(unsigned long loopval)

{

    //volatile unsigned short counter = loopval;

    volatile unsigned long counter = loopval;

    while (counter)

    {

        counter--;

    }

}

void main(void)

{

Int16    looper;

Uint32 check_buff=0;

//////////////////////////////////////////////////////initialize

waitloop(0xfffff); //150ms delay

    //---------------------------

    // PLL initialize

    asm("    *port(#0x1C1F) = #0x0 "); //Clock Configuration MSW reg

    //  program PLL to 100MHz with CLK_SEL = 0

    asm("    *port(#0x1c20) = #0x8BE8 "); //PLL Control 1 reg

    asm("    *port(#0x1c21) = #0x8000 "); //PLL Control 2 reg

    asm("    *port(#0x1c22) = #0x0806 "); //PLL Control 3 reg

    asm("    *port(#0x1C23) = #0x0000 "); //PLL Control 4 reg

    // wait at least 4 milli sec for PLL to lock

    asm("    repeat(0xC350)  ");

    asm("        nop     ");

    asm("    *port(#0x1c1F) = #0x0001 "); // Clock configuration MSW reg

    //---------------------------

    // PLL initialize

    *(volatile ioport Uint16 *)0x0001 = 0x020E;

    asm("   idle");

    // Reset all peripherals

    CSL_SYSCTRL_REGS->PSRCR = 0x0020;

    CSL_SYSCTRL_REGS->PRCR = 0x00BF;

    waitloop(0xfffff); //150ms delay

    //---------------------------

    // all gpio input set

    CSL_GPIO_REGS->IODIR1 = 0xffff;

    CSL_GPIO_REGS->IODIR2 = 0xffff;

    //---------------------------------

    // IRQ initialize

    IRQ_globalDisable();

    IRQ_disableAll();

    IRQ_clearAll();

    //---------------------------------

    // DAC XSMIT HIGH set

    CSL_GPIO_REGS->IODIR2 = 0x0001;  //gpio 16 output set (DAC XSMT)

    CSL_GPIO_REGS->IOOUTDATA2=0x0000; // 1 output

    for(looper=0; looper < CSL_I2S_DMA_BUF_LEN; looper++)

    {

        i2sDmaWriteLeftBuff[looper] = 0;

        i2sDmaReadLeftBuff[looper]  = 0;

        i2sDmaWriteRightBuff[looper] = 0;

        i2sDmaReadRightBuff[looper]  = 0;

    }

/////////////////////////////////////////////////////////////////////////

    PCM5142_init();// DAC set (i2c)

I2S_set(); //I2S set

DMA_set(); // DMA set

    IRQ_globalEnable();

I2S_transEnable(hI2s, TRUE); // I2S_0 Start

    I2S_transEnable(hI2s_2, TRUE); // I2S_2 Start

    while(1)

    {

        UserAlgorithm(); //receive and transmit

    }

}

void UserAlgorithm(void)

{

    int i;

    if(!dmaRxFrameCount)

    {

        /* Start left Rx DMA */

        DMA_start(dmaLeftRxHandle);

        /* Start right Rx DMA */

        DMA_start(dmaRightRxHandle);

    }

    if (dmaRxFrameCount >= 2)

    {

        dmaRxFrameCount=0;

        for (i=0; i<CSL_I2S_DMA_BUF_LEN; i++)

        {

            i2sDmaWriteLeftBuff[i]  = i2sDmaReadLeftBuff[i];

            i2sDmaWriteRightBuff[i] = i2sDmaReadRightBuff[i];

        }

        /* --- Insert algorithm here --- */

    }

    if(!dmaTxFrameCount)

    {

        /* Start left Tx DMA */

        DMA_start(dmaLeftTxHandle);

        /* Start right Tx DMA */

       DMA_start(dmaRightTxHandle);

    }

    /* Clear DMA frame count */

    if(dmaTxFrameCount>=2)

    {

        dmaTxFrameCount = 0;

    }

}

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Thanks