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TCI6638K2K: How to configure DIMM for DDR3A

Part Number: TCI6638K2K

Hi Keystone Team,

A customer of mine is having a few issues bringing up the DDR3A on their TCI6638K2K. The eval board has a DIMM for DDR3A, so the driver settings are different.

Is there a document that explains how to configure it?

They have the following documents already:

  • Keystone II DDR3 Initialization, SPRABX7
  • K2 DDR3 Register Calc v1p60.xlsx spreadsheet
  • Keystone II Architecture DDR3 Memory Controller SPRUHN7C

They're looking for an explanation for filling out the spreadsheet with correct values.

Thanks,

Barend

  • Barend,

    Does the customer board containing TCI6638K2K the accept UDIMMs?  The DDR Controller and PHY within the TCI6638K2K must be properly configured for the SDRAMs attached.  This will vary as different UDIMMs are installed.  The UDIMMs contain a SPD (serial programmable device) that communicates over an I2C port.  This is required by JEDEC.  The values needed to properly configure the DDR Controller and PHY are contained in this SPD.  If you are using Linux, the Uboot code normally would perform this read and configuration prior to using the SDRAM.

    Tom

  • Hi Tom,

    Just wanted to update and say the customer got the board up and running:

    "We performed some overnight testing without issue. No UDIMM sockets, just on-board DDR.

    We did have a problem with random failures pointing to the DDR3, but it turned out to be oscillation on the 1.5V supply. With that fixed, the CPU and software developers are happy."

    However they did have a follow up question, is there a non-DIMM driver for the DDR3B bank?

    Thanks,
    Barend
  • Hi, Barend,

    U-boot reads the DIMM SPD info and program PLL, EMIF, and PHY parameters based on the info read. If not using the SPD info, then it must be properly configured as Tom said. DDR3B is not supported in Linux ProcSDK, and there isn't a driver for it.

    Rex

  • Barend,

    The XTCIEVMK2X Evaluation Module is implemented with a SO-DIMM on DDR3A and discrete SDRAMs on DDR3B.  Therefore, the demo software provided should show an example configuration for DDR3B.  In all cases, the Controller and PHY must be properly configured for the SDRAMs attached.  Please refer to the DDR3 Initialization appnote and the REG_CALC worksheet.

    Tom