On DM385, once HDVPSS LCD(Pinmux enabled) will lead ISS's output abnormal(urgency issue)

gzz

Intellectual 765 points

Other Parts Discussed in Thread: DM385

dell all.

We Got a serious and strange issue or bug on DM385 platform.

Firstly, plsease let me show you some details and core jobs on DM385。

Our core software architecture and code is referenced from IPNC RDK.

The main image processing flow include 3 parts: ISS capture, image-process, HDVPSS display. blow as the details for each part.

ISS capture: the raw image is captured from a sensor by CSI2 interface, the resolution is (1800*1080), then the data is flowed into IPIPEIF->IPIPE->RSZ as ISS TRM said, finally we got a UYUV image(1024*600) from DDR3.

Captured image process: for captured image, we will do some simple image-enhanced algorithm, the final processed output image still is 1024*600, but the format will be YUYV.

HDVPSS display: for processed image, this 1024*600 image(YUYV) will display on HDMI(DM385 self-supported-IP) and LCD(DVO1) by HD VENC_D, the display image format is RGB888.

Now the problem is coming, for hdvpss display, we found that if we only use HDMI to display our image ,all is perfect. but once we enable pinmux for LCD(RGB888), the display exception will comes, some random red blocky stripes will occurs on our image(include hdmi path and dvo1-lcd path), we can only sure that those stripes had appeared when ISS resize output to sdram, so ISS is the issue's source. then once disable all pinmux for LCD, the hdmi display will return to normal.

So we are so strange that why enabled pinmux for LCD(RGB) will lead unknown ISS's processing exception, finally lead our display's mistake.

here is the LCD pinmux for HDVPSS, if below enabled, the issue will comes:

REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AB4) = 0x00040000+0x1; /* vout1_fid_mux1 */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B2C) = 0x00040000+0x1; /* vout1_clk */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B30) = 0x00040000+0x1; /* vout1_hsync */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B34) = 0x00040000+0x1; /* vout1_vsync */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B38) = 0x00040000+0x1; /* vout1_avid */

REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AB0) = 0x00060000; /* vout1_b_cb_c[0] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AAC) = 0x00040000; /* vout1_b_cb_c[1] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B98) = 0x00060000+0x1; /* vout1_b_cb_c[2] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B3C) = 0x00040000+0x1; /* vout1_b_cb_c[3] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B40) = 0x00040000+0x1; /* vout1_b_cb_c[4] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B44) = 0x00040000+0x1; /* vout1_b_cb_c[5] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B48) = 0x00040000+0x1; /* vout1_b_cb_c[6] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B4C) = 0x00040000+0x1; /* vout1_b_cb_c[7] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B50) = 0x00040000+0x1; /* vout1_b_cb_c[8] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B54) = 0x00040000+0x1; /* vout1_b_cb_c[9] */

REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AA0) = 0x00040000; /* vout1_g_y_yc[0] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0A9C) = 0x00060000; /* vout1_g_y_yc[1] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B8C) = 0x00060000+0x1; /* vout1_g_y_yc[2] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B58) = 0x00040000+0x1; /* vout1_g_y_yc[3] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B5C) = 0x00040000+0x1; /* vout1_g_y_yc[4] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B60) = 0x00040000+0x1; /* vout1_g_y_yc[5] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B64) = 0x00040000+0x1; /* vout1_g_y_yc[6] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B68) = 0x00040000+0x1; /* vout1_g_y_yc[7] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B6C) = 0x00040000+0x1; /* vout1_g_y_yc[8] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B70) = 0x00040000+0x1; /* vout1_g_y_yc[9] */

REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AA8) = 0x00040000; /* vout1_r_cr[0] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0AA4) = 0x00040000; /* vout1_r_cr[1] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B94) = 0x00040000+0x1; /* vout1_r_cr[2] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B90) = 0x00060000+0x1; /* vout1_r_cr[3] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B74) = 0x00040000+0x1; /* vout1_r_cr[4] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B78) = 0x00040000+0x1; /* vout1_r_cr[5] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B7C) = 0x00040000+0x1; /* vout1_r_cr[6] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B80) = 0x00040000+0x1; /* vout1_r_cr[7] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B84) = 0x00040000+0x1; /* vout1_r_cr[8] */
REG32_DK(CSL_TI814x_CTRL_MODULE_BASE_DK + 0x0B88) = 0x00040000+0x1; /* vout1_r_cr[9] */

here is some exceptional picture: