CCS/TMS320C6455: Ethernet Cannot work in 100Mb/s mode!

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BR
Tsvetolin Shulev

Hi,

Can you elaborate what TI software package and test example application for this? Is there some configuration you can force the EMAC port in 1G or 10/100 Mb mode?

Regards, Eric

Hi,

    Here's the part of my code. I can see my sample code can get the link speed and duplex mode correctly, but when configure the emac parameter, Only set the rgmii mode, and duplex mode.

There's no any code to configure the emac speed. (I don't know it is necessary or not, because the status register of emac already show the correctly link speed and duplex mode ).  Thank u.

First: Set the auto negotiation bit and reset the phy.

---------------------------------------------------------------------------

Uint32 MDIO_initPHY( Handle hMDIO, volatile Uint32 phyAddr )
{
MDIO_Device *pd = (MDIO_Device *)hMDIO;
Uint32 ltmp1;
Uint32 i,ack;

/* Switch the PHY */
pd->phyAddr = phyAddr;

/* There will be no link when we're done with this PHY */
pd->LinkStatus = MDIO_LINKSTATUS_NOLINK;

/* Shutdown all other PHYs */
ltmp1 = MDIO_REGS->ALIVE ;
for( i=0; ltmp1; i++,ltmp1>>=1 )
{
if( (ltmp1 & 1) && (i != phyAddr) )
{
PHYREG_write( PHYREG_CONTROL, i, PHYREG_CONTROL_ISOLATE |
PHYREG_CONTROL_POWERDOWN );
PHYREG_wait();
}
}

/* Reset the PHY we plan to use */
PHYREG_write( PHYREG_CONTROL, phyAddr, PHYREG_CONTROL_RESET );
PHYREG_waitResultsAck( i, ack );

/* If the PHY did not ACK the write, return zero */
if( !ack )
return(0);

/* Settings for Broadcom phys */
if ( macsel == RGMII )
{
/* Put phy in copper mode */
PHYREG_write( PHYREG_ACCESS, phyAddr, PHYREG_ACCESS_COPPER );
PHYREG_waitResultsAck( i, ack );

/* If the PHY did not ACK the write, return zero */
if( !ack )
return(0);

PHYREG_write( 0x10, phyAddr, 0x0000 ); //GMII Interface
PHYREG_wait();

// Put phy in RGMII mode/in-band status data
if (EMAC_REGS->TXIDVER != 0x000C1207) {
PHYREG_write(PHYREG_SHADOW, phyAddr, PHYREG_SHADOW_INBAND);
PHYREG_waitResultsAck( i, ack );
}

// If the PHY did not ACK the write, return zero
if( !ack )
return(0);

#if 0
// Override gtxcdly so it's low - it's still needed on EVM
PHYREG_write( PHYREG_ACCESS, phyAddr, 0x8C00 );
PHYREG_waitResultsAck( i, ack );

// If the PHY did not ACK the write, return zero
if( !ack )
return(0);
#endif

}
if ( macsel == CSL_DEV_DEVSTAT_MACSEL_GMII )
{
/* Put phy in copper mode */
PHYREG_write( PHYREG_ACCESS, phyAddr, PHYREG_ACCESS_COPPER );
PHYREG_wait();

/* If the PHY did not ACK the write, return zero */
if( !ack )
return(0);
}

/* Setup for our next state */
pd->phyState = PHYSTATE_RESET;
pd->phyStateTicks = 0; /* Reset timeout */

return(1);
}

----------------------------------------------------------------------------------------------------------------

then anto negotiaion the link speed and wait for the auto-negotiation completely.

---------------------------------------------------------------------------------------------------------------

/* Read the STATUS reg to check autonegotiation capability */
PHYREG_read( PHYREG_STATUS, pd->phyAddr );
PHYREG_waitResults( tmp1 );

if ( (macsel == GMII) || (macsel == RGMII) )
{
PHYREG_read( PHYREG_EXTSTATUS, pd->phyAddr );
PHYREG_waitResults( tmp1gig );
}

/* See if we auto-neg or not */
if( (pd->ModeFlags & MDIO_MODEFLG_AUTONEG) &&
(tmp1 & PHYREG_STATUS_AUTOCAPABLE) )
{
/* We will use NWAY */

/* Advertise 1000 for supported interfaces */
if ( (macsel == GMII) || (macsel == RGMII) )
{
tmp1gig >>= 4;
tmp1gig &= PHYREG_ADVERTISE_FD1000;

PHYREG_write( PHYREG_1000CONTROL, pd->phyAddr, tmp1gig );
}

/* Shift down the capability bits */
tmp1 >>= 6;

/* Mask with the capabilities */
tmp1 &= ( PHYREG_ADVERTISE_FD100 | PHYREG_ADVERTISE_HD100 |
PHYREG_ADVERTISE_FD10 | PHYREG_ADVERTISE_HD10 );

/* Set Ethernet message bit */
tmp1 |= PHYREG_ADVERTISE_MSG;

/* Write out advertisement */
PHYREG_write( PHYREG_ADVERTISE, pd->phyAddr, tmp1 );
PHYREG_wait();

/* Start NWAY */
PHYREG_write( PHYREG_CONTROL, pd->phyAddr, PHYREG_CONTROL_AUTONEGEN );
PHYREG_wait();

PHYREG_write( PHYREG_CONTROL, pd->phyAddr,
PHYREG_CONTROL_AUTONEGEN|PHYREG_CONTROL_AUTORESTART );
PHYREG_wait();

/* Setup current state */
pd->ModeFlags |= MDIO_MODEFLG_NWAYACTIVE;
pd->phyState = PHYSTATE_NWAYSTART;
pd->phyStateTicks = 0; /* Reset timeout */

-----------------------------------------------------------------------------------------------------------------------------

when complete, I can see the value of the related register is correct. duplex and 100Mb link speed.

-----------------------------------------------------------------------------------------------------------------------------

/*
* Here we are waiting for NWAY to complete.
*/

/* Read the STATUS reg to check for "complete" */
PHYREG_read( PHYREG_STATUS, pd->phyAddr );
PHYREG_waitResultsAck( tmp1, ack );
if( !ack )
{
MDIO_initStateMachine( pd );
break;
}
if( !(tmp1 & PHYREG_STATUS_AUTOCOMPLETE) )
goto CheckTimeout;

/* We can now check the negotiation results */

if ( (macsel == GMII) || (macsel == RGMII) )
{
PHYREG_read( PHYREG_1000CONTROL, pd->phyAddr );
PHYREG_waitResults( tmp1gig );
PHYREG_read( PHYREG_1000STATUS, pd->phyAddr );
PHYREG_waitResults( tmp2gig );
}

PHYREG_read( PHYREG_ADVERTISE, pd->phyAddr );
PHYREG_waitResults( tmp1 );
PHYREG_read( PHYREG_PARTNER, pd->phyAddr );
PHYREG_waitResults( tmp2 );
/*
* Use the "best" results
*/
tmp2 &= tmp1;

/* Check first for 1 Gigabit */
if( (tmp1gig & PHYREG_ADVERTISE_FD1000) && (tmp2gig & PHYREG_PARTNER_FD1000) )
pd->PendingStatus = MDIO_LINKSTATUS_FD1000;
else if( tmp2 & PHYREG_ADVERTISE_FD100 )
pd->PendingStatus = MDIO_LINKSTATUS_FD100;
else if( tmp2 & PHYREG_ADVERTISE_HD100 )
pd->PendingStatus = MDIO_LINKSTATUS_HD100;
else if( tmp2 & PHYREG_ADVERTISE_FD10 )
pd->PendingStatus = MDIO_LINKSTATUS_FD10;
else if( tmp2 & PHYREG_ADVERTISE_HD10 )
pd->PendingStatus = MDIO_LINKSTATUS_HD10;
/*
* If we get here the negotiation failed
* We just use HD 100 or 10 - the best we think we can do
*/
else if( tmp1 & PHYREG_ADVERTISE_HD100 )
pd->PendingStatus = MDIO_LINKSTATUS_HD100;
else
pd->PendingStatus = MDIO_LINKSTATUS_HD10;

pd->phyState = PHYSTATE_LINKWAIT;

----------------------------------------------------------------------------------------------------------

and then configure the emac

----------------------------------------------------------------------------------------------------------

if( mdioStatus == MDIO_EVENT_LINKDOWN || mdioStatus == MDIO_EVENT_LINKUP )
{
MDIO_getStatus( hMDIO, &phy, &linkStatus );

/* On a new link, set the EMAC duplex */
if( mdioStatus == MDIO_EVENT_LINKUP )
{
if( linkStatus == MDIO_LINKSTATUS_FD10 ||
linkStatus == MDIO_LINKSTATUS_FD100 ||
linkStatus == MDIO_LINKSTATUS_FD1000 )
{
CSL_FINST( EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_FULLDUPLEX, ENABLE );

if ( macsel == CSL_DEV_DEVSTAT_MACSEL_RMII )
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIIDUPLEXMODE, FULLDUPLEX );
}
else
{
CSL_FINST( EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_FULLDUPLEX, DISABLE );

if ( macsel == CSL_DEV_DEVSTAT_MACSEL_RMII )
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIIDUPLEXMODE, HALFDUPLEX );
}

if( linkStatus == MDIO_LINKSTATUS_FD1000 )
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_GIG, ENABLE );

if(( (linkStatus == MDIO_LINKSTATUS_HD10 ) ||
( linkStatus == MDIO_LINKSTATUS_FD10 )) &&
( macsel == CSL_DEV_DEVSTAT_MACSEL_RMII ))
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIISPEED, 2_5MHZ );

if(( (linkStatus == MDIO_LINKSTATUS_HD100 ) ||
( linkStatus == MDIO_LINKSTATUS_FD100 )) &&
( macsel == CSL_DEV_DEVSTAT_MACSEL_RMII ))
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIISPEED, 25MHZ );

/* The following 2 settings apply only to PG 2.0 */
if ( macsel == CSL_DEV_DEVSTAT_MACSEL_RMII ) /* Take RMII out of reset */
CSL_FINST(DEV_REGS->EMACCFG, DEV_EMACCFG_RMIIRST, RELEASE );

if ( macsel == CSL_DEV_DEVSTAT_MACSEL_RGMII ) /* Put RGMII in forced link mode */
CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RGMIIEN, DISABLE );

/* Now that we have a link, send any queued packets */
while( !pi->TxFree )
HwPktTxNext( pi );
}

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Hi, Eric

      Thanks a lot, I will check it.

Regards, Alvin

Alvin,

Have you got chance to try it?

Regards, Eric

Hi Eric,
I've tried, but the problem is still exsits. I use the sample "c6455_emac_echo", it shows that the DSP can receive the packet, but the count is not match which is showed on PC. I don't know the information shows on ccs console screen means the DSP can receive the packet correctly, or just means the DSP can receive the data, but we don't know the data is corrrect or not.