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CCS/TMS320C6748: How do I configure two i2s signals that are connected to the McAsp bus properly?

Part Number: TMS320C6748

Tool/software: Code Composer Studio

Hi

I have a full array microphone projects that use tmsc6748 、2 aic3106 and 4 microphones .
The structure diagram is shown below:


Every two microphones are connected to 3106,The i2s data is passed through axr12 and axr14 to tmsc6748. The both 3106 work fine.
C6748 prvide mclk、bclk and frame clock to 2 codecs.I use EDMA to receive data on the bus.
If I active one 3106 ,6748 can receive data from microphone.But when I activate two devices at the same time, C6748 can no longer receive any interrupt.

How do I configure two i2s signals that are connected to the McAsp bus properly?

  • There are some additions,here is the mcasp bus  initialization.

    Can anyone help me to find the wrong configuration?

    /************************************************************************
    **  filename:
    **  target:  C6748 dsp
    **  Tools:   Code Composer Studio Version 5.5
    **  Author: ty
    **  ------------------------------------------------------------------------
    **  History:
    **        Created on: 2018-6-4
    **  ------------------------------------------------------------------------
    **  Function:mcasp BUS init
    **  ------------------------------------------------------------------------
    **  This software is the property of innotrik Technology Stock Co.,Ltd.
    **  All Rights Reserved
    ****************************************************************************
    */
    #include "TL6748.h"
    
    #include "edma_event.h"
    #include "interrupt.h"
    #include "soc_OMAPL138.h"
    #include "hw_syscfg0_OMAPL138.h"
    
    #include "codecif.h"
    #include "mcasp.h"
    #include "edma.h"
    #include "psc.h"
    #include "uartStdio.h"
    #include "dspcache.h"
    
    #include "aic3106_init.h"
    #include "mcasp_init.h"
    
    /****************************************************************************/
    /*                                                                          */
    /*              Macro                                                     */
    /*                                                                          */
    /****************************************************************************/
    // McASP Rx
    #define MCASP_XSER_RX                         (12u)
    #define MCASP_XSER_RX1			  (14u)
    // McASP  Tx
    #define MCASP_XSER_TX                         (11u)
    #define MCASP_XSER_TX1                        (13u)
    
    #define I2S_SLOTS                             (2u)
    #define SLOT_SIZE                             (16u)
    // Word size <= Slot size
    #define WORD_SIZE                             (16u)
    #define NUM_SAMPLES_PER_AUDIO_BUF             (320u)
    #define NUM_SAMPLES_PER_MOVE                  (160u)
    /****************************************************************************/
    /*                                                                          */
    /*              global                                                    */
    /*                                                                          */
    /****************************************************************************/
    
    /****************************************************************************/
    /*                                                                          */
    /*              McASP  out                                              */
    /*                                                                          */
    /****************************************************************************/
    void OutputSample(unsigned int outData)
    {
    	McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, 11, outData);
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*              McASP  in                                            */
    /*                                                                          */
    /****************************************************************************/
    unsigned int InputSample(void)
    {
    	return (McASPRxBufRead(SOC_MCASP_0_CTRL_REGS, 12));
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*               McASP Rx init	                                */
    /*                                                                          */
    /****************************************************************************/
    void McASPI2SRxConfigure(unsigned char wordSize,unsigned char slotSize,
    		unsigned int slotNum, unsigned char modeDMA)
    {
    	// Reset
    	McASPRxReset(SOC_MCASP_0_CTRL_REGS);
    
    	switch(modeDMA)
    	{
    		case MCASP_MODE_DMA:
    			// enable FIFO
    			McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
    
    			// set word and slot size
    			McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
    								MCASP_RX_MODE_DMA);
    			break;
    		case MCASP_MODE_NON_DMA:
    			// set word and slot size
    			McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
    								MCASP_RX_MODE_NON_DMA);
    			break;
    	}
    
    	// syn,TDM form、 slot Num,edge
    	McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, slotNum, MCASP_RX_FS_WIDTH_WORD,
    			              MCASP_RX_FS_INT_BEGIN_ON_RIS_EDGE);
    
    	// set clock source 
    	McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 23, 0);
    	McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
    	McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
    						  0x00, 0xFF);
    
    	// enable  RxClkSync
    	McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
    
    
    	//enable  rx slot
    	McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, (1 << slotNum)-1);
    
    	// Serializer 12 14
    	McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
    	McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX1);
    	// pin and direction
    	McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
    
    	McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_RX));
    	McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AXR(MCASP_XSER_RX1));
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*                      McASP Tx     	                                */
    /*                                                                          */
    /****************************************************************************/
    void McASPI2STxConfigure(unsigned char wordSize,unsigned char slotSize,
    		unsigned int slotNum, unsigned char modeDMA)
    {
    	// reset
    	McASPTxReset(SOC_MCASP_0_CTRL_REGS);
    
    	switch(modeDMA)
    	{
    		case MCASP_MODE_DMA:
    			// enable FIFO
    			McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
    
    			// set word 、 slot size
    			McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
    								MCASP_TX_MODE_DMA);
    			break;
    		case MCASP_MODE_NON_DMA:
    
    			McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
    								MCASP_TX_MODE_NON_DMA);
    			break;
    	}
    
    	// syn,TDM form、 slot Num,edge
    	McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, slotNum, MCASP_TX_FS_WIDTH_WORD,
    			               MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
    
    	// clock source
    	McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 23, 0);
    	McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
    	McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
    						  0x00, 0xFF);
    
    	//enable  TxRxClkSync
    	McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
    
    	// 使能 发送 slot
    	McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, (1 << slotNum)-1);
    
    	// Serializer 11 13
    	//McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
    	McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX1);
    	// pin and direction
    	McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
    
    	McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AFSX
    				                                   | MCASP_PIN_ACLKX
    				                                   | MCASP_PIN_AHCLKX
    				                                   | MCASP_PIN_AXR(MCASP_XSER_TX)
    				                                   | MCASP_PIN_AXR(MCASP_XSER_TX1));
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*               McASP mode selection	                                */
    /*                                                                          */
    /****************************************************************************/
    void McASPI2SConfigure(unsigned char transmitMode, unsigned char wordSize,
    		unsigned char slotSize, unsigned int slotNum, unsigned char modeDMA)
    {
    	// enable McASP PSC
    	PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_MCASP0, PSC_POWERDOMAIN_ALWAYS_ON,
    			 PSC_MDCTL_NEXT_ENABLE);
    
    	if(transmitMode & MCASP_TX_MODE)
    	{
    		McASPI2STxConfigure(wordSize, slotSize, slotNum,  modeDMA);
    	}
    
    	if(transmitMode & MCASP_RX_MODE)
    	{
    		McASPI2SRxConfigure(wordSize, slotSize, slotNum,  modeDMA);
    	}
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*              McASP int init		                                */
    /*                                                                          */
    /****************************************************************************/
    void McASPIntSetup(unsigned int cpuINT, void (*userISR)(void))
    {
    	IntRegister(cpuINT, userISR);
    	IntEventMap(cpuINT, SYS_INT_MCASP0_INT);
    	IntEnable(cpuINT);
    }
    
    /****************************************************************************/
    /*                                                                          */
    /*              Start Rx and Tx			                            */
    /*                                                                          */
    /****************************************************************************/
    void I2SDataTxRxActivate(unsigned char transmitMode)
    {
    	if(transmitMode & MCASP_TX_MODE)
    	{
    		McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
    
    		McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
    
    		McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
    
    		McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
    		McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX1, 0);
    	}
    
    	if(transmitMode & MCASP_RX_MODE)
    	{
    		McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL);
    
    		McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
    
    		McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
    	}
    }

    here is the edma initialization

    //Rx paRAM 
    static struct EDMA3CCPaRAMEntry const rxDefaultPar =
           {
               (unsigned int)(EDMA3CC_OPT_SAM  | OPT_FIFO_WIDTH), 	// Opt     
               (unsigned int)SOC_MCASP_0_DATA_REGS, 		// Source address
               (unsigned short)(BYTES_PER_SAMPLE), 			 // aCnt      
               (unsigned short)(1), 				// bCnt        
               (unsigned int)rxBuf0, 				// target address
               (short) (0), 					//  bIdx
               (short)(BYTES_PER_SAMPLE), 				   //  bIdx 
               (unsigned short)(PAR_RX_START * SIZE_PARAMSET), 	    // 40 paRAM
               (unsigned short)(0), 				    // bCnt reload in 
               (short)(0), 						    // cIdx
               (short)(0), 						    // cIdx
               (unsigned short)1 					    // cCnt
           };
    ......
    ......
    
    /****************************************************************************/
    /*
    ;** athuer:ty
    ;** :void InitMcaspEdma(void)
    ;**--------------------------------------------------------------------------------------
    
    ----------------
    ;** date:
    ;** version:  0.0
    ;** description: Mcasp and Edma init
    ;** history:
                                                                             */
    /****************************************************************************/
    static void InitMcaspEdma(void)
    {
    	EDMA3Init(SOC_EDMA30CC_0_REGS, 0);
    	EDMA3IntSetup();
    
    	//ch 0 Rx,ch 1 Tx
    	EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
    						EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);
    	EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
    						EDMA3_CHA_MCASP0_RX, EDMA3_CHA_MCASP0_RX, 0);
    
    	I2SDMAParamInit();
    
    	McASPI2SConfigure(MCASP_BOTH_MODE, WORD_SIZE, SLOT_SIZE, I2S_SLOTS, MCASP_MODE_DMA);
    
    	EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
    						EDMA3_TRIG_MODE_EVENT);
    	EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
    						EDMA3_TRIG_MODE_EVENT);
    
    	I2SDataTxRxActivate(MCASP_BOTH_MODE);
    }
    
    
    
    

  • Hi,

    Which Processor SDK RTOS version are you using?

    Best Regards,
    Yordan
  • Thanks,I don't use any rtos .
  • Ok, I've asked the TMS320C674x sw team to help. They will post their feedback directly here.

    Best Regards,
    Yordan
  • thanks for your help!I will follow the message here.
  • I detected a rovrn flagin the RSTATregister 

    So,it get be a data overflow happend. 

  • Issue has been resolved in the following thread: e2e.ti.com/.../707647