I've set up a timer 3 to generate an interrupt every 1ms (auto-reload mode, 32kHz base clock, 0xffffffdf TLDR value, only overflow interrupt enabled) for DSP.
But examining TSCL and TSCH registers in the infinite loop after "Task_sleep(1000)" instruction I've found that timer interrupt in sysbios is running two times faster.
Looking deeper in the issue it looks like spurious interrupt occurs while timer 3 "ticking" from 0xffffffdf to 0xffffffe0 state. If TLDR register value changed from 0xffffffdf to 0xffffffe0 then no extra interrupt is observed.
I didn't find anything about timer 3 and interrupts in errata and the timer seems to be configured properly.
Why spurious interrupt is observed?
UPD: I'm using bios 6.32.01.38 from the Easy Software Development Kit (EZSDK) 5_02_01_59 for the DM816x/C6A816x/AM389x Aug 29 2011.