API solutions Forum - Recent Threads

AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Yi Yang — Thu, 14 May 2026 10:15:06 GMT

Part Number: AM625

Hi:

Now, I am using FPGA to collect data. My plan is to use DMA to read data from the fixed source address of the FPGA, and then transfer the data to the memory. The data format used by the FPGA is FIFO, that is, after reading 16-bit data from a fixed address, reading the next data, the FPGA will refresh the data at this fixed original address.
Now I don't know which DMA method to use for data transfer. Using dma_memcpy method, where both the source address and the destination address are incremented does not meet my requirements. PSI-L DMA cannot be used.

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Bin Liu — Wed, 27 May 2026 19:41:37 GMT

Hi Yi,

What you need is traditional DMA_DEV_TO_MEM transfer using BCDMA, however, the dmaengine drivers in the current kernel (v6.18.x) does not support it for AM625x devices.

A couple years ago, a customer had a similar request and I added the DMA_DEV_TO_MEM support in the kernel k3_udma driver. The following link has all the details.

AM625: Rerouting interrupt to DMA event and DMA_DEV_TO_MEM channel selection

RE: AM6422: SCI Client timeout value

Jun Tu — Mon, 25 May 2026 13:34:48 GMT

I have another question, what is the time resolution of this SystemP_WAIT_FOREVER. each count is for 1 nanosecond? or each counter is cpu cycle?

Thanks

AM6422: SCI Client timeout value

William Durocher — Mon, 25 May 2026 13:12:53 GMT

Part Number: AM6422

We wish to have a definite timeout value for the SCI Client messages. We currently use

SystemP_WAIT_FOREVER, which is defined as ((uint32_t)-1). We want to replace it with a vlue that will allow us to have a more defined timeout.

What is the maximum expected timeout for a message to sciclient server to be defined as timed out?

MSPM0G3507: MSPM0G3507/3107 cannot enter BSL mode

jiaqi wang — Wed, 20 May 2026 10:22:11 GMT

Part Number: MSPM0G3507

Requirement: I need to use MSPM0G3507/3107 as the target and upgrade it using I2C on another MCU.

Problem: When MSPM0G3507/3107 receives I2C data 0X22 sent by the host MCU, it will call invokeBSLAsm() to enter BSL, but the current phenomenon is that it still cannot enter BSL after calling.

Judgment method: The following is the timing sequence of the host MCU:

1 i2c_ti_write_register(0X22,0x55); Send 0x22 request to enter bsl,

2 i2c_ti_write_register(0xBB,0xAA);

status = i2c_ti_read_register(I2C_TI_FRAME_REG);

Determine if the status is 0x51 to determine if it has entered BSL,

The following is the I2C processing code for MSPM0G3507/3107

case DL_I2C_IIDX_TARGET_RXFIFO_TRIGGER:

i2c_reg_value = DL_I2C_receiveTargetData(I2C_INST);

if(i2c_reg_value == 0x22) {invokeBSLAsm();}

The PIN pins configured for MSPM0G3507/3107 are SCL (PB2) and SDA (PB3). These two pins are connected to the I2C of the host MCU. Do I have any other syscfg configurations that prevent me from accessing BSL?

RE: MSPM0G3507: MSPM0G3507/3107 cannot enter BSL mode

Sal Ye — Thu, 21 May 2026 05:42:58 GMT

Hi Jiaqi,

The flow looks correct to me.

Can you confirmed where the MCU running? You can toggle a simple GPIO (LOW->HIGH->LOW) after main app start to indicate MCU are not running in BSL mode.

[quote userid="700450" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1647667/mspm0g3507-mspm0g3507-3107-cannot-enter-bsl-mode"]The PIN pins configured for MSPM0G3507/3107 are SCL (PB2) and SDA (PB3).[/quote]

So, I assume have configured NVM settings to assign new pin to BSL I2C PIN. (default is PA0/PA1).

B.R.

Sal

RE: MSPM0G3507: MSPM0G3507/3107 cannot enter BSL mode

jiaqi wang — Wed, 20 May 2026 10:25:08 GMT

I2C_TI_FRAME_REG = 0x80

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Swargam Anil — Wed, 20 May 2026 08:58:53 GMT

Hello Yi,

I am routing your query to Linux expert to better assist you for the above quires .

Regards,

Anil.

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Yi Yang — Wed, 20 May 2026 07:20:19 GMT

Hi Ani,

Currently, I am developing a Linux driver and need to read data from the fixed registers of GPMC and store it in DDR. I need to apply for a DMA_DEV_TO_MEM type channel, but I'm currently not sure how to obtain this channel. The driver code in Linux is as follows:

dma_cap_mask_t mask;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
struct dma_chan *channel = dma_request_channel(mask, NULL, NULL);

struct dma_slave_config cfg;
struct dma_async_tx_descriptor *tx = NULL;

cfg.direction = DMA_DEV_TO_MEM;
cfg.src_addr = gpmc_bus_phy_addr;
cfg.dst_addr = dma_phy_addr;
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
cfg.dst_maxburst = 1;
cfg.src_maxburst = 1;
ret = dmaengine_slave_config(channel, &cfg);
tx = dmaengine_prep_slave_single(data->m_channel,
dma_phy_addr,
data_size,
DMA_DEV_TO_MEM,
DMA_CTRL_ACK | DMA_PREP_INTERRUPT);

tx->callback = fpga_dma_complete;
tx->callback_param = data->m_wait;

dmaengine_submit(tx);
dma_async_issue_pending(channel);

wait_for_completion(data->m_wait);

After executing the above code, the following error occurred.

udma_prep_slave_sg: chan3 is for MEM_TO_MEM, not supporting DEV_TO_MEM；

Regards,

Yi.

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Swargam Anil — Wed, 20 May 2026 05:28:51 GMT

Hello Yi,

PSRAM and NOR memories are memory-mapped to the SOC.

So, you can create BCDMA channels to transfer data from GPMC to destination memory and vice versa.

You can look at the FAQ below, where I have used one BCDMA channel for reading data from GPMC to destination memory.

[FAQ] : How to trigger DMA with the help of GPIO on AM64X/AM243 and AM62X devices ?

Similarly, you can create one more channel for transferring data from source memory to GPMC memory.

Please let me know if you face any issues.

Regards,

Anil.

CODECOMPOSER: Add breakpoint using symbol CCS 20.40

Silviu-Bogdan Stoian — Mon, 18 May 2026 12:17:58 GMT

Part Number: CODECOMPOSER

Is this possible:
Placing a breakpoint at a particular line with inputs as function name and at a particular line ( not at line number ); e.g. In func1{ a=b ;} I want to provide input to the API as : setbp( func1, "a=b;").

Can this be done through the existing APIs in CCS 20.40?

RE: CODECOMPOSER: Add breakpoint using symbol CCS 20.40

Ki — Tue, 19 May 2026 19:17:05 GMT

How about creating a C label in your code and then setting the breakpoint on that label? This is a technique I see others have done in the past for a similar usecase.

RE: CODECOMPOSER: Add breakpoint using symbol CCS 20.40

Silviu-Bogdan Stoian — Tue, 19 May 2026 06:04:34 GMT

The idea is to be able to set a breakpoint inside a function at a line that contains syntax "a=b", as an example. The approach where you input the line number does not work very well for us when code changes (automation tests break).

RE: CODECOMPOSER: Add breakpoint using symbol CCS 20.40

Ki — Mon, 18 May 2026 21:18:36 GMT

[quote userid="700029" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1646810/codecomposer-add-breakpoint-using-symbol-ccs-20-40"]Placing a breakpoint at a particular line with inputs as function name and at a particular line ( not at line number );[/quote]

Are you looking to have it so that the brekapoint (when triggered) will call a function in your program? If not, can you provide more details on your exact use case?

Thanks

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Yi Yang — Fri, 15 May 2026 07:47:42 GMT

Hi Anil：

The communication between GPMC and FPGA has been developed and tested successfully.

After the FPGA collects the data, the ARM needs to read the data from the fixed GPMC bus address.

The data is approximately 100MB.I plan to use DMA to read the data into the DDR, thereby reducing the CPU usage rate.

I'm not sure if the GPMC of AM6254 supports DMA.I couldn't find any relevant information in the TRM.

I discovered that AM6254 does not support the DMA mode through another post.

e2e.ti.com/.../am625-q1-dma-cycle-with-gpmc-module-in-non-multiplexed-mode

Regards,

Yi.

RE: AM625: AM6254 How to use DMA to transfer the fixed source address data of GPMC to the memory

Swargam Anil — Thu, 14 May 2026 12:09:36 GMT

Hello Yi Hang,

Many customers use GPMC for your requirement.

On the SOC side, configure it for NOR or PSRAM memory type. Then on the FPGA, you need to write custom logic to read data over the GPMC.

FYI, GPMC is a parallel interface. With this interface, you can read data from the FPGA over GPMC with DMA and without DMA is also supported.

If you want more details, you can refer to the GPMC chapter in the TRM.

Regards,

Anil.

AM2434: AM243X Series image conbine hex file

ShInGuk Kim — Thu, 14 May 2026 08:12:19 GMT

Part Number: AM2434

Hello. TI guys!

I am a firmware developer at Autonics in Korea.

I am using the AM243x series, and I am currently evaluating development on the LP board.

We are using a single core, R5-0, with different memory jump addresses configured for each application, and we are running Ethernet/IP and Profinet programs.

I am trying to combine the SBL(tiimage), APP(tiimage), and XIP (appimage_xip) into a single HEX file.

At first, I tried to create a BIN file. Although it worked, there was a large amount of unused space between the application areas, which caused the file size to become extremely large.

So, I am trying to create a HEX file without unused empty spaces.

owever, although I combined multiple files (SBL(tiimage), APP(tiimage), and XIP (appimage_xip)) into a single HEX file, it does not run.

Is there any way to combine multiple images, including XIP, into a single HEX file?

Also, I configured the Ethernet/IP XIP start address as 0x60100000 and the Profinet XIP start address as 0x60300000.

When actually merging the images, what offset addresses should be used?

Please reply to me.

Thanks. Best Regards.

RE: PSPICE-FOR-TI: PSPICE-FOR-TI dowloand problems

Mihnea Horbuli — Mon, 11 May 2026 11:11:06 GMT

Unfortunately I have the same problem, is this a global issue?

PSPICE-FOR-TI: PSPICE-FOR-TI dowloand problems

Burak Kaya — Sat, 09 May 2026 11:28:43 GMT

Part Number: PSPICE-FOR-TI

I want to download PSPICE-FOR-TI, but the download link returns a 404 error. Could you help me with this?

RE: PSPICE-FOR-TI: PSPICE-FOR-TI dowloand problems

Jacky Chen — Sun, 10 May 2026 01:31:15 GMT

could you help me to fix this bug as soon as possible.

RE: AM623: Clarification on Functional Safety Assumptions mentioned in FSM

Neelima Muralidharan — Thu, 07 May 2026 02:58:47 GMT

Hello Augustene,

Please see responses below:

1) Yes your understanding is correct.

2) Regarding system configuration checks - the intention here is that for the components other than the SOC itself in the system, the configuration checks and all needed safety checks will be performed by system integrator. An example is the external PMIC or an external discrete watchdog etc. For the SoC itself, the safety manual provides guidance on the needed configuration checks.

3) Your understanding is correct. Additionally, if the board needs to be powered off or reset due a fault on the board itself which means the availability of the safety function is impacted. This availability itself is not considered a safety function.

4) This does not really contradict SA_1. According to SA_1, if power sequencing requirements are provided by the data sheet, those must be followed. However, the power sequencing itself is not considered as a safety function. Safety function begins only after active power state is reached.

5) No it is not a violation. The start up verifier is what we recommend as part of "runs any required integrity checks". This is recommended before entering the steady state safety function.

6) Same as #2 above.

Regards,

Neelima

AM623: Clarification on Functional Safety Assumptions mentioned in FSM

Augustene Pasala — Thu, 23 Apr 2026 12:29:24 GMT

Part Number: AM623

Hi Team, I went through the section “4.10 Functional Safety Constraints and Assumptions” of “Functional Safety Manual for AM62x”. Thought to get clarification from TI on the some of the items listed there.

Could you please help with the response to these, please note "[AP]" text refers to our understanding of the safety assumption.

SA_1 “The system integrator shall follow all requirements in the datasheet for the component”

[AP] : Our understanding of this assumption is, the datasheet “AM62x Sitara™ Processors” revision “SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025”, shall be reviewed by system integrator and incorporate all the requirements such as PIN connectivity, Hardware Requirements, Power Supply Requirement etc. Is this correct ?

SA_11 “The system integrator shall perform system configuration and implementation checks.”

[AP]: Can TI provide more clarification on this.

SA_12 “Availability of system function is not a safety requirement. When the system is off, the system is considered to be in a safe state.”

[AP]: the understanding is, if the board on which AM6321 is running, if it is powered off then there would not be impact on the System to which the board is connected. An example is, if AM6231 is driving an actuator, even if the actuator is not driven as the board is powered off, the system should be in safe state. ( Assuming that there is redundancy built such that actuator is driven by other module)

SA_13 “The power sequencing requirements of the device are not considered to safety-critical.”

[AP] : This appears to contradict with SA_1 as the datasheet has few requirements related to power supply sequencing. Can TI provide more insights into the SA_13.

SA_18 “The safety function is not begun until the software enables the function after the device successfully completes the start-up sequence, runs any required integrity checks, and is in a normal mode of operation.”

[AP]: We use QNX safety RTOS for our applications, in the recent versions of RTOS, QNX recommended to use startup verifier that ensures system is set up properly before control is given to RTOS. The start-up verifier is part of start-up sequence and in the process if it finds any faults, it takes device to designed safe state. Does this violate the statement in SA_18 that safety function is not begun.

SA_11 “The system integrator shall perform system configuration and implementation checks.”

[AP]: Can TI provide more clarification on this.

Thanks & REgards

Augustene

AM263P4-Q1: NIST Standards

Sravya Kalluri — Tue, 07 Apr 2026 05:53:02 GMT

Part Number: AM263P4-Q1

Hi Team ,

I would like to get confirmation on the standards currently being used for AM263P4 and F29H85x.
I have attached a file below that outlines the security functions and the latest standards currently in use. Kindly confirm whether the security features in AM263P4 and F29H85x comply with these standards. If not, please advise on the additional changes required.
featureVsStandard.xlsx

RE: AM263P4-Q1: NIST Standards

Aditya Singal — Mon, 04 May 2026 15:58:00 GMT

Hi Sravya,

FIPS 140-3 is a system based solution, although we believe that we are FIPS 140-3 ready by we haven't gotten the compliance standard for that yet.
RSA(encryption, decryption) follows NIST FIPS 186-5 and not NIST SP 800-56B.

Thanks and Regards,
Aditya Singal

DLPC3478: ghost in API developing.

Lun Zhao — Thu, 30 Apr 2026 20:22:17 GMT

Part Number: DLPC3478

Hi officer,

I am testing dlpc347x_samples.c in DLPC-API-1.12.

I simplified it and find the trouble : When I use "DLPC34XX_ReadRgbLedMaxCurrent/WriteRgbLedCurrent" after "DLPC34XX_ReadControllerDeviceId", the device ID is not available; when I comment out the "DLPC34XX_ReadRgbLedMaxCurrent/WriteRgbLedCurrent", I can get the device ID which is 11.

I am using Mingw v4.8.1 x64 compiler with this command:

gcc -std=gnu99 -DWIN32 -g -Iapi -Isamples main.c api\dlpc_common.c api\dlpc34xx.c api\dlpc347x_internal_patterns.c samples\cypress_i2c.c third_party\cyusbserial\cyusbserial.lib -o main.exe

I attached my code here, it is simplified from dlpc347x_samples.c

main.c

cyusbserial.lib and cyusbserial.dll was replaced from here:

https://github.com/mayeranalytics/cyusbserial/tree/master/cypress/mingw32/x86_64

The reason I replaced them is that I want to use 64bit program.

I appreciate any suggustions.