https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/en-USTelligent Community 13https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1658019/am5728-am5728-linux-sdk-roadmap-and-kernel-upgrade-strategy/6394970Thu, 25 Jun 2026 10:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1a0039da-fc81-4aa6-af5f-f46c5efebd3fShiv RaiDear TI Support Team, Thank you for the detailed response regarding the AM57xx software roadmap, the transition to the CIP 6.12 SLTS kernel baseline, and the upcoming Q4 2026 upstreaming targets. To help us finalize our long-term product maintenance architecture and clarify our internal engineering resource allocation, we have two specific follow-up questions regarding the future support delivery model: 1. Clarification on "Internal Releases via CI/CD Process" You mentioned that future software models will shift to internal releases shared with customers as part of TI's internal CI/CD process. Could you clarify the eligibility criteria to access these internal CI/CD releases? Are these builds available to all commercial customers developing on the AM57xx platform, or are they restricted based on target production volume/account tier? What are the formal technical or account requirements required to ensure our engineering team is included in this distribution pipeline? 2. Maintenance Responsibility for the ti-linux-6.12.y Branch Regarding the Super Long-Term Stable (SLTS) 6.12 kernel baseline: Will Texas Instruments actively maintain and push periodic stable/security updates (backported from the CIP/mainline stable community) directly into the public ti-linux-6.12.y git branch at git.ti.com ? Alternatively, should customers expect that the current branch is functionally frozen from TI's side, meaning we are expected to manually pull, merge, and test CIP security updates/patches into our local kernel tree ourselves? Our objective is to ensure we align our engineering pipelines smoothly with TI's updated delivery workflows. Thank you for your continued guidance. Best regards,https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1658429/tms570lc4357-not-able-to-get-csp-for-halcogen-generated-drivers/6394848Thu, 25 Jun 2026 08:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8060dd9d-4b6c-4a53-8803-71396d37b94djagadish gundavarapuHi Deepak, Please do follow below thread: (+) RM46L852: Request access to SafeTI Diagnostic Library v2.4.0 Compliance Documents for RM46L852 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums -- Thanks & regards, Jagadish.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1658429/tms570lc4357-not-able-to-get-csp-for-halcogen-generated-driversThu, 25 Jun 2026 07:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:58675a08-7266-4e5d-ae8d-1a636c5b2d46Deepak MPart Number: TMS570LC4357 Other Parts Discussed in Thread: HALCOGEN Hello, We would need CSP for TMS570LC4357 MCU halcogen generated drivers. Kindly let us know how we have to proceed.HALCoGenRM46L852TMS570LC4357https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1658019/am5728-am5728-linux-sdk-roadmap-and-kernel-upgrade-strategy/6394054Wed, 24 Jun 2026 18:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:67644a52-a27b-4968-b190-b7a7cebb5823Josue Zamitiz-AyalaHello Shiv Rai , The latest SDK 11.1 (<-- see release notes) is the last official SDK release from TI for AM57xx. The model will change into only internal releases that can be shared with the customer as part of our internal CI/CD process. As part of TI’s commitment to use the community supported long term stable releases, we have updated the AM57 Processor SDK 11.1 release to latch on to the Linux kernel version 6.12 which is identified for super long-term stable(SLTS) kernel. SLTS kernel 6.12 will be supported till Mid-2035, by CIP project. Customers may directly engage with CIP for super long-term support . In upstream, AM57x is supported, and TI is committed to maintain this platform in upstream code branches Most of features are available in upstream code base and remaining features TI is committed to upstream (These features pulled into SDK while upstreaming is in progress) PRU/HSR/PRP support Upstreaming in progress[1] Target 4Q 2026 VIP driver support – Already up-streamed Early boot and late attach support – In progress These modules above are the major differences. I will have to ask our development team for information on Linux 7.x, but i believe the CIP comment above is the plan. -Josuehttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1655294/am62a7-am62a7-occasional-startup-failure-of-c7x/6393161Wed, 24 Jun 2026 07:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7177ac7f-d806-47fc-8698-0eaeabbbf4c4Meet ThakarHi Yangtian, Could you please provide steps to reproduce this issue, so that I can test this out at my end and will try to figure out what should be the right way to resolve this. Meanwhile you can try the fix suggested here: RE: AM62A7: Power-on probability does not display the camera image and see if that resolves the issue at your end as well. Best Regards, Meet.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1658019/am5728-am5728-linux-sdk-roadmap-and-kernel-upgrade-strategyWed, 24 Jun 2026 06:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4fb04227-79f5-425a-bc66-7a04ef321e07Shiv RaiPart Number: AM5728 Hello TI Team, We are evaluating the long-term software strategy for an AM5728-based product currently running Processor SDK Linux 6.03. We are considering migration to Processor SDK Linux 11.01 or Latest Upstream kernel and would appreciate guidance on the following topics: 1. AM57x Software Roadmap Is TI planning a future Processor SDK Linux release for AM57x devices based on a Linux 7.x kernel series (for example, Linux 7.1.x)? If yes, is there an estimated timeline or roadmap for such a release? 2. TI SDK Kernel vs Upstream Kernel We understand that SDK 11.01 uses: Linux 6.12 (ti-linux-6.12.y) Could TI help us understand: What are the major differences between the TI kernel and the corresponding upstream Linux 6.12 kernel for AM57x? Which AM57x features depend on TI-specific kernel patches? 3. SDK 11.01 with Future Linux 7.x Kernel If future security requirements necessitate migration to a Linux 7.x kernel (e.g., Linux 7.1.x): Can SDK 11.01 Yocto infrastructure be used with a newer upstream Linux kernel? What AM57x-specific components would likely require porting when moving from ti-linux-6.12.y to a future Linux 7.x kernel? Would TI recommend staying on the TI-maintained kernel branch or migrating to an upstream kernel for long-term maintenance? Our objective is to maintain a secure and supportable software platform for a long-lifecycle commercial product. Thank you for your guidance.AM5728https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1656091/tms320f280025c-tms320f280025c-flash-api-source-code-request/6391914Tue, 23 Jun 2026 13:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:44b67507-0af2-4a8d-9106-d528b922e2f1Hakan TOPUZHello Sira, First of all, thank you for your interest. We are developing the bootloader in accordance with DO-178 processes. In this context, we need the source code or DO-178 certificate. Does the Flash API library have a DO-178 certificate? If so, could you please share the certificate? Thankshttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1656091/tms320f280025c-tms320f280025c-flash-api-source-code-request/6391805Tue, 23 Jun 2026 11:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bc89ee68-6c92-4021-bc22-411b1a02ccb2Sira Rao80Hi Hakan, It turns out that our secure resources database for the Flash API source was missing the F28002x Flash API source. I have put in a request to update the asset. Once it's updated, I can send you a request link. However, is it possible for you to just use the Flash API library in your custom bootloader, without needing the source? Thanks, Sirahttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1655294/am62a7-am62a7-occasional-startup-failure-of-c7x/6385828Wed, 17 Jun 2026 09:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:379323df-6f35-4c2b-9720-63b85b978976Xu(SH) Liuplease connect associated C7 dsp core's Jtag and CCS to check the status of C7 with program loaded as symbol and provide backtrace.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1656091/tms320f280025c-tms320f280025c-flash-api-source-code-requestWed, 17 Jun 2026 07:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ab01190d-2b4a-4c16-9d53-dc9ab3f6a1c2Hakan TOPUZPart Number: TMS320F280025C I am a member of the Software Development Team. We are currently working with the TMS320F280025C microcontroller from the C2000 family and developing a custom bootloader. Therefore, we would like to request access to the source code of the Flash API related to this device. Can you help us with this? NOTE: We already have an NDA agreement in place.tms320f280025Chttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1654776/am625-q1-the-issue-regarding-the-debugp_log-printing-function/6385634Wed, 17 Jun 2026 07:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:32b31e33-0dc6-4dd7-8a84-2a5483fc5b29Tushar ThakurHi, Your image1 shows the garbage character in CIO but the image2 does not shows the same. Is the same application running on both cases? What have changed between image1 and image2? Can you also share your UART configuration settings from Sysconfig? Regards, Tusharhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1654776/am625-q1-the-issue-regarding-the-debugp_log-printing-function/6385514Wed, 17 Jun 2026 05:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f6c10f0-b9bc-4ef5-acf7-4b8cffac5e7dVaibhav KumarHi, There are some checks which may not be enabled in SysConfig of your application. I have assigned this ticket to another expert who can help answer this. Regards, Vaibhavhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1655294/am62a7-am62a7-occasional-startup-failure-of-c7x/6383773Tue, 16 Jun 2026 05:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c867fc30-2cb3-43e3-921d-474f6ee1557eyangtian yiThank you Meet, The version of mcu_plus_sdk we using is 11_01_00_16 Best Regards, Yangtianhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1655294/am62a7-am62a7-occasional-startup-failure-of-c7x/6383768Tue, 16 Jun 2026 05:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3c3c49d4-9bda-4877-9aff-b079d3c93a1aMeet ThakarHi, Please allow me some time to check this internally and get back to you. Best Regards, Meet.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1655294/am62a7-am62a7-occasional-startup-failure-of-c7xMon, 15 Jun 2026 07:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b944f404-4064-4348-9eba-8b68a2d1c63eyangtian yiPart Number: AM62A7 During the development of our product software, we utilize the SBL boot mode. We have observed that during multiple repeated restarts, the IPC communication between A53 and C7x sometimes fails to establish at startup, with the specific error shown in the figure below. However, at this time, the IPC communication between A53 and other cores, such as MCU R5, is normal. I found a link on the forum where the situation encountered by the user is similar to ours. Furthermore, he ultimately found a potential solution to the problem. AM62A7: Power-on probability does not display the camera image - Processors forum - Processors - TI E2E support forums We are unsure whether this solution is reasonable and hope that TI experts can provide an answer based on our error report and the issues mentioned in the linkAM62A7https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1652204/dlp473te-is-dmd-park-command-for-dlpc84xx-available/6381942Mon, 15 Jun 2026 01:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:62a769c3-91a9-448f-a7cc-c0f9684e4b8aKevin RiveraHi Collin, Welcome to E2E! You can use the command "Sequence Enable" in Control Program. If the sequence is disabled, the DMD will be parked. Enabling it will unpark it. Could you link the programmers guide you are using to verify this information is present? Thank you, Kevin Riverahttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1654776/am625-q1-the-issue-regarding-the-debugp_log-printing-functionFri, 12 Jun 2026 03:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:31e98a85-1040-4601-9f49-2b7584b55b42zhaoneng dengPart Number: AM625-Q1 Other Parts Discussed in Thread: SYSCONFIG I have a question that I'd like to ask you for advice One: I can print garbled characters in CCS using the vprintf_ function, but cannot print in the serial port tool as shown in the figure in Attachment 1. Two: DebugP_log debug cannot be accessed and there is no print either. As shown in Figure 2 of Attachment. The current UART configuration is as follows : /* UART Driver Parameters */ UART_Params gUartParams [ CONFIG_UART_NUM_INSTANCES ] = { { .baudRate = 115200 , .dataLength = UART_LEN_8, .stopBits = UART_STOPBITS_1, .parityType = UART_PARITY_NONE, .readMode = UART_TRANSFER_MODE_BLOCKING, .readReturnMode = UART_READ_RETURN_MODE_FULL, .writeMode = UART_TRANSFER_MODE_BLOCKING, .readCallbackFxn = NULL , .writeCallbackFxn = NULL , .hwFlowControl = FALSE , .hwFlowControlThr = UART_RXTRIGLVL_16, .transferMode = UART_CONFIG_MODE_POLLED, .skipIntrReg = FALSE , .uartDmaIndex = - 1 , .intrNum = 219U , .intrPriority = 4U , .operMode = UART_OPER_MODE_16X, .rxTrigLvl = UART_RXTRIGLVL_8, .txTrigLvl = UART_TXTRIGLVL_32, .rxEvtNum = 0U , .txEvtNum = 0U , }, }; I would like to ask: 1. Why doesn't DebugP_log take effect? 2. How to print normally?SYSCONFIGAM625-Q1https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1653211/mspm0g3507-configuring-write-protection-on-mspm0g3507/6378400Wed, 10 Jun 2026 23:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1f66f003-85fc-47b8-a724-9f9c32ac9268JD CrutchfieldHello Reshma, Overall, it looks like you have a good understanding of the SWP, but I want to clarify some of the password questions. First question up top: On G3507 there is no password protected regions of flash. I don't know that we have that on any MSPM0. The memory is either write protected or not, but there is no read or execute protections on this specific device. Some of the larger devices do have these options, but I still don't believe there is a password based memory access option. Could you please clarify: Whether the static write protection configuration described above is correct for protecting the application region beginning at 0xA000. I see 0xFFFF001F. This does protect memory about the first 32kB as you mentioned(0x0000-0x8000 are unprotected), and each bit is 8kB, so the 0x1F at the end will add 5x 8kb to the lower 32kB giving us a starting address as -> protected memory 0x1.2000 to 0x1.FFFF (end of memory.) Please double check my math there. Whether the observed behavior after executing password-protected Mass Erase is expected. Mass erase is a DSSM command, and so it's going to bypass SWP and still erase all of the memory but not Nonmain, so then you SWP would get applied to blank memory. I'm unsure of the communication errors after mass erase. I have seem the DSSM commands, especially the special ones with passwords, sometimes cause issues with programmer communication and cause the USB cable to be unplugged and re-plugged. It's been a while since I've seen this, so possible it's been fixed already. Whether password-protected Mass Erase affects NONMAIN memory and security configuration regions. As mentioned, Mass Erase says it will still erase the main memory even if SWP is going to be applied, but it won't change NONMAIN. This is because the DSSM command is processed by the bootcode after a reset, before it applies the Nonmain SWP settings. If you don't want this, you should disable Mass Erase. Whether the SEC_AP access failure after the erase operation is a known behavior. No known, but as mentioned, sometimes the tools mess up at this step. If you power cycle and can connect and the device is as you expect then everything worked. Whether any additional CCS or UniFlash configuration is required when validating password-protected Mass Erase and Factory Reset functionality. I haven't tried password mass erase through CCS in a while. I know the process you are using works for password based debug. There is also a MSPM0 Factory Reset web tool: https://dev.ti.com/gallery/view/TIMSPGC/MSPM0_Factory_Reset_Tool/ver/1.0.2/ It allows you to type in your custom password for Mass Erase and Factory reset and execute these DSSM commands. Overall, I really think you have it but maybe the tool was just acting up. I did want to point out there there are multiple different passwords possible. Factory Reset and Mass Erase can each have their own unique password. Debug can have it's own password for connecting. The BSL can also have it's own password for updating via it. All of these can also be fully disabled for more security. Passwords available for all device access, but not for accessing specific regions of memory. Hope this clarifies. JDhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1653835/tcan1463evm-fault-analysis/6377684Wed, 10 Jun 2026 15:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:120a962a-1462-4a2b-81d4-7c79af497528Michael IkwuyumHi Xiaochuan, It sounds like VSUP is not applied and would recommend to probe all pins (especially supply and input pins) to double confirm, similar to the EVM user's guide, thanks. Best Regards, Michaelhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1653211/mspm0g3507-configuring-write-protection-on-mspm0g3507/6376904Wed, 10 Jun 2026 04:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:17eb0a12-afa1-4815-8dec-0752f19491deReshma RoohiSelva Kumaran Rajan