https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/en-USTelligent Community 13https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1681428/lp-em-cc35x1-cc35xx-psa-crypto-is-a-combined-ecdsa-ecdh-key-policy-supportedFri, 11 Sep 2026 07:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e2246132-868a-4048-8ab9-4d6b982326baVishnu BabuPart Number: LP-EM-CC35X1 Other Parts Discussed in Thread: SHA-256 , SYSCONFIG Hi TI Team, I am working with a CC35XX device using SimpleLink Wi-Fi SDK 10.10.01.08 and the PSA Crypto API. I need to use a single persistent P-256 ECC key pair for two operations: ECDSA P-256 + SHA-256 signing ECDH P-256 key agreement This is based on an existing implementation on another platform where the same PSA key is configured with a primary ECDSA algorithm and ECDH as the enrollment/secondary algorithm. The key attributes I am using are: psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_set_key_type(&attributes, PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)); psa_set_key_bits(&attributes, 256); psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_DERIVE); psa_set_key_algorithm(&attributes, PSA_ALG_ECDSA(PSA_ALG_SHA_256)); psa_set_key_enrollment_algorithm(&attributes, PSA_ALG_ECDH); psa_set_key_lifetime(&attributes, PSA_KEY_LIFETIME_PERSISTENT); I have tested both psa_generate_key() and psa_import_key() . 1. psa_import_key() result Before importing the key, the attributes are: Algorithm = 0x06000609 // PSA_ALG_ECDSA(PSA_ALG_SHA_256) Algorithm2 = 0x09020000 // PSA_ALG_ECDH Usage = 0x00005400 // SIGN_HASH | DERIVE Lifetime = 0x00000001 // PSA_KEY_LIFETIME_PERSISTENT The import succeeds. However, after retrieving the key attributes using: psa_get_key_attributes() I get: Type = 0x00007112 Bits = 256 Usage = 0x00005400 Algorithm = 0x06000609 Algorithm2 = 0x06000609 Lifetime = 0x00000001 So the ECDH enrollment algorithm appears to be changed from: PSA_ALG_ECDH to: PSA_ALG_ECDSA(PSA_ALG_SHA_256) during key import/storage. 2. ECDSA operation Using the imported persistent key: psa_sign_hash(key_id, PSA_ALG_ECDSA(PSA_ALG_SHA_256), ... ); works successfully. 3. ECDH operation using the same key When I try: psa_raw_key_agreement(PSA_ALG_ECDH, device_key_id, peer_public_key, peer_public_key_length, shared_secret, shared_secret_size, &shared_secret_length); the operation fails with: PSA_ERROR_NOT_PERMITTED (-133) 4. Standalone ECDH test To verify that ECDH itself is supported and working, I created two separate temporary P-256 key pairs with: psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DERIVE); psa_set_key_algorithm(&attributes, PSA_ALG_ECDH); psa_set_key_lifetime(&attributes, PSA_KEY_LIFETIME_VOLATILE); ECDH works successfully in both directions, and both sides produce the same 32-byte shared secret. Therefore, standalone P-256 ECDH through the CC35XX HSM is working. My question Is a single ECC P-256 key with combined ECDSA + ECDH usage supported by the CC35XX PSA Crypto implementation? Specifically, is the following policy supported? Key type: ECC P-256 key pair Usage: PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_DERIVE Primary algorithm: PSA_ALG_ECDSA(PSA_ALG_SHA_256) Enrollment/secondary algorithm: PSA_ALG_ECDH If it is supported, could you please advise: Is there a specific key attribute configuration required for combined ECDSA + ECDH? Is psa_set_key_enrollment_algorithm() supported for persistent CC35XX keys? Is there a limitation in the CC35XX HSM/key store that causes alg2 to be replaced by the primary algorithm during psa_generate_key() or psa_import_key() ? Is there a recommended way to configure a single persistent key for both ECDSA signing and ECDH key agreement? If combined policy is not supported , is the recommended approach to use two separate persistent ECC key pairs—one for ECDSA and one for ECDH? SysConfig configuration One additional observation: in my .syscfg project configuration, under: Crypto Drivers → TI Security Drivers I currently have PSA Crypto + KeyStore and RNG added. I have not explicitly added separate SHA2, ECDSA, ECDH, or AES-GCM driver instances. My application will require: SHA-256 TRNG ECDSA ECDH AES-256-GCM Could the absence of these individual Crypto Driver instances affect PSA Crypto functionality on CC35XX, or are these operations automatically provided through the PSA Crypto/HSM implementation after psa_crypto_init() ? I would appreciate any guidance on the supported combined-key policy and the required SysConfig configuration. Thanks.SHA-256SYSCONFIGLP-EM-CC35X1https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1680966/am62a7-q1-dlinferer-run-call-blocks/6480301Fri, 11 Sep 2026 01:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:332b186b-892f-432b-b5ce-96395c51c7abJay GoyalHi Junliang, Can you please run the /opt/vx_app_arm_remote_log.out script in the background? This should give more verbose C7x logs and help in figuring out what is going wrong. Can you also try to provide the GDB stack trace at the time the error happens? Some details on your pipeline would be appreciated. As in, if you are using VPAC(ISP, LDC or MSC nodes), are you running multiple instances of TIDL models, etc. Regards, Jayhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1680688/tms320f2800156-q1-flashdriver/6479306Thu, 10 Sep 2026 10:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e632a33c-5b62-4be6-8f6c-66f0a4e7328dArpit VarahmihirHi Youjun, Let me look into it and get back to you. Regards Arpithttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1680966/am62a7-q1-dlinferer-run-call-blocksThu, 10 Sep 2026 02:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:95dbc017-a27d-47d3-bcdd-af70a25751dbjunliang xiaPart Number: AM62A7-Q1 Calling DLInferer::run() requires setting the export TIDL_RT_DDR_STATS=0 variable; otherwise, after normal calls for a period of time, it will block in DLInferer::run(). After setting the export TIDL_RT_DDR_STATS=0 variable and calling DLInferer::run(), if the systemctl restart command is used to restart the service program that calls the DLInferer::run() interface, it will block in DLInferer::run() after 20 to 40 restarts. The resource release issues within the service program have already been investigated, and no abnormal resource release issues have been found.Advanced Driver Assistance Systems (ADAS)AM62A7-Q1https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1679485/dlpc964-how-to-check-the-internal-temperature/6478102Wed, 09 Sep 2026 16:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1c5c4924-a011-4492-9415-af2e6fd3aeadTristan BottoneHello Shinkichi, The DLPC964 controller does not provide internal die-temperature readback via I²C. The complete register map in the DLPC964 Datasheet (DLPS167A) (Tables 6-9 through 6-47) defines all available I²C-accessible registers and does not include any register for die-temperature monitoring or readback. Therefore, a live DLPC964 die-temperature value cannot be obtained through the I²C interface. The only temperature-related information TI publishes for the DLPC964 is in the Absolute Maximum Ratings table, which lists a junction temperature limit (Tj: -65°C to +125°C), and the thermal characteristics table, which lists thermal resistance values (RθJA, RθJB, RθJC). Those numbers are meant for board-level thermal design and worst-case rating checks during layout, not for reading the chip's actual operating temperature at runtime. What you can measure is the DMD temperature. On the DLPLCRC964EVM, the GUI's DLPC964 Tab has a "Temperature (Celsius)" field showing both DMD and DMD Board temperature. These readings come from a TMP411 temperature sensor mounted on the DMD board itself, not from inside the DLPC964 chip. The DLPC964 just reads that sensor over I2C and passes the value along to the GUI. If you'd rather read this temperature directly in your own code instead of through the EVM GUI, you can communicate with the TMP411 sensor directly over I2C using its own register map. If you specifically need the temperature of the DLPC964 die itself, there's currently no built-in way to do that. The only option would be adding an external temperature sensor near the DLPC964 on your board. Best Regards, Tristan Bottonehttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1679484/dlpc964-how-to-check-the-internal-temperature/6477849Wed, 09 Sep 2026 13:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7a3061a1-2624-4992-8918-a2bcb3ade17aTristan BottoneSeems like this question was duplicated. I am going to close this ticket, and will reply on the original forum listed here: https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1679485/dlpc964-how-to-check-the-internal-temperature Regards, Tristan Bottonehttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1680688/tms320f2800156-q1-flashdriverWed, 09 Sep 2026 08:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cd5ca6ba-501f-45da-99a9-8293ade71204youjun zhangPart Number: TMS320F2800156-Q1 hi expert: In the UDS requirements, flashdriver.hex (a separate file stored in RAM) is needed to perform flash erase and write operations. Firstly, in BootLoader, can commutation is used to receive flashdriver.hex. After successful reception, the erase and write operation functions are called to update the app.hex. Is there any relevant routine or solution introduction? How to use the flashAPI library file to create a flashdriverTMS320F2800156-Q1https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00/6475424Tue, 08 Sep 2026 03:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a780612b-25f9-4626-aa44-1a2b0ed541a1ayyappa THi, How can we test the PBIST instance "SDL_PBIST_INST_WKUP_PBIST1" in SBL Stage 1, can you point me the reference. thank you.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678274/am2434-regarding-the-ethercat-subdevice-the-processing-time-for-each-process-is-longer-than-expected/6474768Mon, 07 Sep 2026 08:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:29f7d6d3-3d7e-47b8-b064-c91ed858c449Aaron ThomasHi, The assigned expert is currently out of office. Please expect a response by tomorrow or Wednesday. [quote userid="615798" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678274/am2434-regarding-the-ethercat-subdevice-the-processing-time-for-each-process-is-longer-than-expected"]1. Is it possible to communicate with process data sizes of up to 1 KB (as in Test Case 2) using the desired cycle time and synchronization method? If so, please provide an estimate of the maximum configurable process data size under these conditions.[/quote] As per EtherCAT SubDevice: Datasheet , the maximum process data payload size is 1KB, with the cycle time as low as 50us: While we are at 1KB Process Data test case, can you provide more details on the state transition failure for 1KB PD? Are you seeing any value in AL Status Code (ESC Reg 0x0134)? [quote userid="615798" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678274/am2434-regarding-the-ethercat-subdevice-the-processing-time-for-each-process-is-longer-than-expected"]2. Regarding the BESync0Task and BEPDItask in Test Case 1, the execution times seem quite long relative to the configured process data size; are these considered reasonable execution times?[/quote] I'll let the expert comment on this. Regards, Aaronhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00/6473499Fri, 04 Sep 2026 11:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:32bb0d05-09c8-40f7-a0cd-667719ae9107ayyappa THi Nihar Potturu, thank you for you response, there is on issue with the POST when i read the "HW_RD_REG32(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_POST_STAT); " it is returning just "0" in result. But as per the TRM if i toggle the BOOTMODE15 = 1 the SoC is not getting booted. And also there is no PBIST test for GPU if i add GPU instance i'm encounter some error in the latest SDK. thakn you, ayyappa Thttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1679484/dlpc964-how-to-check-the-internal-temperatureFri, 04 Sep 2026 09:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:43403bfc-dbfe-4330-a3e3-23b623adeec8Shinkichi KuroiwaPart Number: DLPC964 Please explain how to check the internal temperature of the DLPC964.DLPC964https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1679485/dlpc964-how-to-check-the-internal-temperatureFri, 04 Sep 2026 09:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2d882c72-bb03-46ad-a07f-cbb2ef9e37a3Shinkichi KuroiwaPart Number: DLPC964 Other Parts Discussed in Thread: DLPLCRC964EVM , TMP411 Please explain how to check the internal temperature of the DLPC964.DLPLCRC964EVMDLPC964TMP411https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678719/am62p-for-inquiries-regarding-dss-sending-issues/6470619Wed, 02 Sep 2026 11:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2dfdcbe9-a57a-45d4-aad0-c064019d7bf8Divyansh MittalHi QW, Is the expectation to also send CRC data post frame scan-out? This is not supported, and I also do not see the uescase. There are multiple CRC generated per VP and VID, how much data do you expect to be sent, and who is inferring this data? I don't think any panel comes with this capability (do let me know if there is one). Whole purpose of safety is to have interrupts get handled by a real time core, not sure how this approach works.https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678719/am62p-for-inquiries-regarding-dss-sending-issuesWed, 02 Sep 2026 10:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:12e910ee-f633-4d7c-abec-6ed68846d686Q WPart Number: AM62P Hello As shown in the following figure, a CRC check value needs to be added at the end of each frame of the sent video stream, and this value needs to be sent in the HFP. May I ask if our DSS supports this method? If supported, what configurations and operations need to be doneAM62PBody Electronics & Lightinghttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00/6470364Wed, 02 Sep 2026 07:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d4f2624c-d71c-48bf-a066-9106051acd51Nihar PotturuHi Ayyappa, [quote userid="715521" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00"] Provide us details regarding the POST test how can we trigger it from the HS_FS devices and How can we check the result from the SBL itself.[/quote] POST is enabled and run default in the HW. You can monitor the WKUP_CTRL_MMR_CFG0_POST_STAT register directly from SBL. [quote userid="715521" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00"]Is running MPU PBIST directly from SBL Stage 2 (WKUP R5) supported without requiring a full SoC warm reset afterwards?[/quote] Yes. [quote userid="715521" url="~/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677401/am62p-q1-am62px-a53-core-0-fails-to-boot-after-running-main-and-mpu-pbist-in-sbl-stage-2-mcu-sdk-10-00-00"]Are there specific isolated power-domain reset, clock-gating, or TISCI sequence steps required to completely restore the MPU (Compute Cluster) and MAIN interconnects to a clean operational state after PBIST completes?[/quote] Yes, please check the latest SBL EMMC Linux example. The PBIST test is integrated into this example along with the recovery steps for MPU instances. https://github.com/TexasInstruments/mcupsdk-core-k3/tree/k3_main/examples/drivers/boot/sbl_emmc_linux_multistage/sbl_emmc_linux_stage1/am62px-sk/wkup-r5fss0-0_nortos Regards, Nihar Potturuhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678274/am2434-regarding-the-ethercat-subdevice-the-processing-time-for-each-process-is-longer-than-expectedTue, 01 Sep 2026 08:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8091018d-949c-48ad-b071-4fbf8e0f050e?? ??Part Number: AM2434 Other Parts Discussed in Thread: LP-AM243 Hello to the development team. I am developing software for an EtherCAT subdevice using your LP-AM243 board. We encountered the issue mentioned in the title during the course of development. Environment Board: LP-AM243 SDK: ind_comms_sdk_am243x_2026_00_00_06 (Standard) and MCU+SDK mcu_plus_sdk_am243x_12_00_00_26 Usage Example: 401_simple from EtehrCAT_Subdevice_demo Problem We are attempting EtherCAT communication using DC synchronization with a cycle time of 250 µs. Test Case 1: We confirmed that communication operates normally when the process data size is 14 bytes for input and 18 bytes for output. Test Case 2: We confirmed that communication fails (becomes abnormal) when the process data size is 798 bytes for input and 722 bytes for output. Ideally, we would like to establish communication using a single sub-device with data sizes of up to 1 KB in each direction, as in Test Case 2. Investigation To investigate the issue and check task load, we used FreeRTOS hook functions to monitor the task context and measure task execution times. The results were as follows: Conditions: Cycle time 250 µs, DC synchronization, OP state Test Case 1: BEPDItask: Approx. 74 µs BESync0Task: Approx. 115 µs Appl_LoopTask: Approx. 35 µs Test Case 2: No measurement results available (failed to transition to OP state). Questions 1. Is it possible to communicate with process data sizes of up to 1 KB (as in Test Case 2) using the desired cycle time and synchronization method? If so, please provide an estimate of the maximum configurable process data size under these conditions. 2. Regarding the BESync0Task and BEPDItask in Test Case 1, the execution times seem quite long relative to the configured process data size; are these considered reasonable execution times? Thank you for your assistance. Kind regards,Industrial AutomationLP-AM243AM2434https://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1677977/tms320f280049c-sci-bootloader-txt-file-format-datasheet/6468641Tue, 01 Sep 2026 05:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7137f39e-21ac-43e8-ad29-c77f3bcacc73Arpit VarahmihirHi Nibesh, The .txt file actually is TI’s standard “boot data stream” (used by all C2000 ROM bootloaders: SCI, SPI, I2C, CAN, Parallel), ASCII-hex-encoded for transmission over SCI. It’s generated from your compiled .out file using the hex2000 utility (bundled with the C2000 compiler / CCS Hex Utility). This is added as a post-build step in CCS (Project Properties > CCS Build > Steps > Post-build steps) for both the flash kernel project (flashapi_ex2_sciKernel) and the application project (flashapi_ex3_liveFirmwareUpdate) , both must be in this SCI8 boot format. (TI Hex Conversion Utility guide : https://downloads.ti.com/docs/esd/SPRU513J/Content/SPRU513J_HTML/hex_conversion_utility_description.html ) This is the actual field layout hex2000 packs into the file, one byte per two ASCII-hex characters: Section 4.6..8.1 : TMS320F28004x Real-Time Microcontrollers Technical Reference Manual (Rev. H) There is also a worked example in the TRM ( example 4-1) : SCI boot mode operation specifics ( TRM Section 4.6.7.2) • Only accepts an 8-bit stream — key value must be 0x08AA (a 16-bit stream/key 0x10AA is rejected on SCI boot). • Uses SCI-A autobaud: host sends 'A'/'a', the ROM locks the baud rate against it, then echoes every received byte back to the host so the host can verify each byte landed. Default SCI GPIO options for F280049C are mentioned in Section 4.6.9 of the TRM : Also refer to TMS320F28x Boot Features and Configurations (Rev. A) for boot pin conifg. F28004x-class devices support fully customizable boot mode selection: • Up to 3 Boot Mode Select Pins (BMSPs), each mappable to almost any GPIO, configured via the 32-bit BOOTPIN-CONFIG register (Z1/Z2-OTP-BOOTPIN-CONFIG, or EMU-BOOTPIN-CONFIG in RAM for emulation testing). • A fully custom boot definition table (BOOTDEF, up to 8 entries) replacing the factory default table, configured via Z1/Z2-OTP-BOOTDEF-LOW/HIGH. • We recommend validating your boot config in emulation mode first (writable RAM registers at 0x0D00–0x0D06) since OTP can only be programmed once. • Getting Started with Bootloading on C2000 ™ Microcontrollers Section 4.2.2 walks through the exact zero-pin SCI boot emulation sequence: set EMU-BOOTPIN-CONFIG (0xD00) to 0x5AFF FFFF (disables all BMSPs) and EMU-BOOTDEF-LOW (0xD04) to the SCI boot option value (e.g. 0x0001), then reset. Flash Kernel flow : 1. Device resets into SCI boot mode (BMSPs / BOOTDEF as configured above). 2. ROM SCI bootloader autobaud-locks and loads flashapi_ex2_sciKernel.txt into RAM (kernel must be built with RAM linker config). 3. Kernel takes control, erases the target flash sector(s), and connects with the host again over SCI. 4. Host sends flashapi_ex3_liveFirmwareUpdate.txt (built with Flash linker config) ,same block-size/address/data stream structure and the kernel’s linked Flash API programs each received block. 5. Kernel branches to the application’s entry point once the transfer completes (block-size-0x0000 terminator reached). This RAM-kernel-bridges-to-flash pattern is because ROM bootloaders can only ever load into RAM directly flash kernels are the standard bridge Reference : Serial Flash Programming of C2000 Microcontrollers App Note (SPRABV4) : https://www.ti.com/lit/an/sprabv4i/sprabv4i.pdf Other references: • Live firmware update / bank-swap issue on F280049C (flashapi_ex2 + flashapi_ex3, BANK0/BANK1 swap behavior): https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1383344/tms320f280049c-live-firmware-upgrade-issue • SCI kernel autobaud-lock reliability on F280049C: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1036927/tms320f280049c-ensuring-correct-sci-flash-kernel-loading-to-ram-and-behavio r • General bootloader .txt file-content question on F280049C: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1160370/tms320f280049c-bootloader-file-contents • SCI serial bootloader best-practice thread (F280049C): https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1399366/tms320f280049c-c2000ware-sci-serial-bootloader-example---best-practice • LAUNCHXL-F2800157 CAN flash programming thread (useful cross-reference for the analogous CAN .txt structure): https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1428110/tms320f28388s-customer-bootloader-related-inquiries Regards Arpit Varahmihirhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678001/tms320c6748-g722-2-amr-wb-codec-for-c6x-dsp/6467897Mon, 31 Aug 2026 16:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e369c778-7536-4a32-a090-214552f102adNick SaulnierAM62D is the upcoming processor for audio applications (uses C7 core), replacing C674x (uses C6000 core). At this point in time, we have only released the automotive variant of the part. I do not have an exact timeline for when the general-purpose part will be released. https://www.ti.com/product/AM62D-Q1 AM275x is another part where we have released the automotive variant, and at some point I expect us to release the general-purpose part: https://www.ti.com/product/AM2752-Q1 Regards, Nickhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678001/tms320c6748-g722-2-amr-wb-codec-for-c6x-dsp/6467872Mon, 31 Aug 2026 16:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:58be5a54-4e96-47f5-bf5d-57cef322b8e9Nick SaulnierHello Uwe, Please note that we can no longer provide hardware or software design support for C6748, as per the "limited design support" banner on the product page: https://www.ti.com/product/TMS320C6748 There is a speech codec package available. I am not sure if it has G722.2 codec specifically: TMS320C6748: Proper voice codec pack Regards, Nickhttps://e2e.ti.com/support/enterprise-automation-integration-group/enterprise-automation-integration/f/api-solutions-forum/1678001/tms320c6748-g722-2-amr-wb-codec-for-c6x-dspMon, 31 Aug 2026 13:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4fa10855-10f9-4653-a411-4af5513daf83Uwe HalmPart Number: TMS320C6748 Does TI provide a library for G722.2 Codec for C674x DSPs?AM2752-Q1AM62D-Q1tms320c6748