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CLC001: CLC001

Part Number: CLC001
Other Parts Discussed in Thread: LMH0074

Hi team,

We have a customer inquiring about the supply current for CLC001. Below is the verbatim of his inquiry:

We are now using DVB-ASI, the sender uses the CLC001 driver. The receiver is reserved for the LMH0074. After using the xilinx FPGA for data analysis, it is found that the data is lost, so the LMH0074 is skipped and used directly by AC coupling. Connected to FPGA. The current data analysis is normal, but the FPGA is easily damaged at present, and the FPGA of three receiving devices has been damaged within two weeks. The specific reason cannot be determined now, and I hope to get your help.

The figure below is the connection diagram during our test.

In addition, the output level swing of CLC001 is at least 800mV, while the LVDS level of IO pin input of XILINX FPGA is at most 600mV. Does this have any effect?
If the receiving end is damaged, will it cause damage to the sending end? At present, the equipment at the sending end cannot test the ASI signal.

Problem Description .docx

Thank you in advance.

  • Greetings,

    Typically we should use CLC001 at transmit site while LMH0074 is used on the receiving before the FPGA. I am not sure why we are not using LMH0074 on the receiving side. If there is an issue we should look into this first before we bypass or not use LMH0074.

    CLC001 single ended output is 800mV peak to peak. In your block diagram you are using both P & N. This means FPGA input is at 1600mV - way over its 600mV spec. Potentially this could be the reason why FPGA is damaged. 

    Please note since we are AC coupling, we don't expect damage to the sending end or CLC001.

    Regards,,nasser