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TL16C2552: difference of interrupt behavior between TL16C2552 and PC16552

Part Number: TL16C2552

Dear Technical Support Team,

Let me check the interrupt.
Is it possible to switch between edge sense and level sense for TL16C2552IFN interrupts(INTA and INTB)?

Is there difference of interrupt behavior  between TL16C2552 and PC16552?

■background
I make a send / receive error intentionally, then PCI9050 + PC16552 does not result in an illegal interrupt (normal error handling)
However FPGA PCI Bridge + TL16C2552IFN results in an invalid interrupt at the kernel level

I don't know if it's a kernel or an app, but after some UART initialization,
PC16552 does not keep INTA and  INTB asserted(PC16552 is once asserted and then deassert)
TL16C2552IFN keeps INTA and INTB.

Next plan, I will check PCI9050+TL16C2552IFN. 

Best Regards,

ttd

  • TTD,

    Thank you for your patience on the long holiday weekend in America. An engineer has been notified of this thread and will respond by end of business July 6th.

    Regards,

    Eric Hackett

  • Hi Eric,

    Thank you for your reply.

    I tried PCI9050+TL16C2552IFN, but the same result with FPGA PCI Bridge + TL16C2552IFN.

    ■ Additional questions

    Is the following correct?

    -For TL16C2552IFN, INT is enabled immediately after reset.
    -For PC16552, INT is not enabled immediately after reset.

    According to each URAT data sheet, there are differences in the register and pin states immediately after reset.

    [PC16552]
    8.0 Registers TABLE III. DUART Reset Configuration
    MODEM Control Register
    Master Reset
    0000 0000

    [TL16C2552IFN]
    Table 2. ACE Reset Functions
    Modem control register
    Master reset
    All bits, except bit 3, cleared (6-7 permanent), MCR3 set

    INT
    Master reset MCR3
    Output buffer enabled

    ■ Additional information
    I tried to test UART register of TL16C2552IFN, but INTA and INTB remain asserted even though there is no interrupt factor (IIR = 01).
    Also, if you write 0 to IER, then interrupt signal remains asserted.

    ■Interrupt Enable Register (IER)

    The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an

    interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of

    this register are summarized in Table 3 and are described in the following bullets.

    • Bit 0: When set, this bit enables the received data available interrupt.
    • Bit 1: When set, this bit enables the THRE interrupt.
    • Bit 2: When set, this bit enables the receiver line status interrupt.
    • Bit 3: When set, this bit enables the modem status interrupt.
    • Bits 4 through 7: These bits are not used (always cleared).

    Best Regards,

    ttd

  • Hi ttd,

    "I make a send / receive error intentionally, then PCI9050 + PC16552 does not result in an illegal interrupt (normal error handling)"

    How are you making the error?

    Can you walk me through how you initialize the device? (what values do you write into the registers after reset/power-up?)

    "I tried to test UART register of TL16C2552IFN, but INTA and INTB remain asserted even though there is no interrupt factor (IIR = 01).
    Also, if you write 0 to IER, then interrupt signal remains asserted."

    When are you seeing the INT assert? Is it immediately after reset? or are you doing something else, then check after you did some register read/writes?

    -Bobby