Dear Technical Support Team,
Let me check the interrupt.
Is it possible to switch between edge sense and level sense for TL16C2552IFN interrupts(INTA and INTB)?
Is there difference of interrupt behavior between TL16C2552 and PC16552?
■background
I make a send / receive error intentionally, then PCI9050 + PC16552 does not result in an illegal interrupt (normal error handling)
However FPGA PCI Bridge + TL16C2552IFN results in an invalid interrupt at the kernel level
I don't know if it's a kernel or an app, but after some UART initialization,
PC16552 does not keep INTA and INTB asserted(PC16552 is once asserted and then deassert)
TL16C2552IFN keeps INTA and INTB.
Next plan, I will check PCI9050+TL16C2552IFN.
Best Regards,
ttd