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DP83TD510E: questions related to DP83TD510E and 10Base-T1L

Part Number: DP83TD510E

Hi Team, 

My customer is considering implement 10Base-T1L to their product, they have following questions about 10Base-T1L and DP83TD510E. Please kindly help these. Thanks.

Besides following questions, customer is asking if we can hold a seminar to teach them how to start use DP83TD510E. For example, how should they construct the circuit to use it.

Is it possible? We can discuss via mail for detail. 

1. I think DP83TD510E don't have integrated MAC, do TI have other parts with or without integrated MAC(or on roadmap) for 10Base-T1L besides DP83TD510E?

2. I think 10Base-T1L supports point to point connection, can it connect multiple PHY by daisy-chain connection? Please show us if there's any example. 

3. Is there designated or recommended connector to use for 10Base-T1L?

4. Is there any designation or example of PCB pattern design for TX+,TX-,RX+,RX- for 10Base-T1L?

5. Is there any power IC recommendation for DP83TD510E?

6. Is it not necessary to add something, for example varistor, to suppress noise on communication line? Please let me know if there's any recommendation for noise suppress implementation. 

7.  What is the definition of "short reach" in DP83TD510E datasheet? Less than 200m?

8. I think 10Base-T1L supports PoDL, can DP83TD510E support supplying and receiving power? Please show us if there's any reference design. 

9. For SPE, I think normally capacitor is used for isolation instead of transformer, how can we superimpose power to transmit/receive data line? Is there any example schematic? 

Thanks.

Regards,

Jo

  • Hi Jo,

    1. DP83TD510E does not have an integrated MAC. Any discussions involving roadmap need to be taken under NDA.

    2. Daisy chain should be supported, however multidrop is not supported as multidrop falls under T1S.

    3. We'll get back to you on this question.

    4. I'm not totally clear on this question, if you're looking for an example of PCB routing and implementation you can refer to the EVM: www.ti.com/.../snlu271a.pdf

    5. There's no specific recommendation, as long as the LDO or power device is able to handle the power draw of the PHY it should be ok. You may refer again to the EVM for a reference of how we have implemented our power staging.

    6. Are you referring to noise suppression on the MDI lines? We currently do not have a recommendation for noise suppression on the MDI lines, but we far out reach the 1km defined in the T1L spec without additional components on the MDI.

    7. We'll get back to you on this question.

    8. We'll get back to you on this question.

    9. There's a tradeoff between the transformer and capacitor, which is signal isolation versus size and BOM cost. What do you mean by superimposed power? Is this referencing PoE or PoDL?

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Jo,

    3. There is no designated or recommended connector.

    7. Short reach means 200m for T1L.

    The customer can follow the EVM user guide I linked above to learn how to use the DP83TD510E. I'll reach out via email regarding a seminar.

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Lucas, 

    Thanks for the reply. 

    For question 8, I think DP83TD510E do support supplying and receiving power, but TI have no PSE/PD solution for SPE now, is my understanding correct?

    For questions 9, yes, I meant PoDL. Customer is wondering how can SPE superimpose power to data line if they use capacitor instead of transformer for isolation. I think "PoDL Example" in p.2 of following material is showing this, achieved by PSE/PD before capacitor. Is my understanding correct? 

    https://www.tij.co.jp/jp/lit/wp/snla360/snla360.pdf

    Thanks.

    Regards,

    Jo

  • Hi Lucas, 

    For question 4, customer is asking if impedance control or GND guard ring is needed or not. Is there any material explaining this? 

    4. Is there any designation or example of PCB pattern design for TX+,TX-,RX+,RX- for 10Base-T1L?

    For question 6, yes, customer is referring MDI lines. Customer is asking is there designation or recommendation for capacitor to isolate? 

    6. Are you referring to noise suppression on the MDI lines? We currently do not have a recommendation for noise suppression on the MDI lines, but we far out reach the 1km defined in the T1L spec without additional components on the MDI.

    Customer asked another question, is initial register setting of DP83TD510E-EVM being disclosing? If yes, could you share it ?

    Thanks.

    Regards,

    Jo 

  • Hi Jo,

    We're looking into your questions and will get back to you by Thursday.

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Jo,

    4. The termination scheme should be in the datasheet. They may refer to the EVM as a full PCB example. Yes, the MDI lines should be impedance controlled with a 100 ohm differential impedance.

    6. What configuration are you interested in? The EVM should power up without any additional configuration.

    The initial settings are described in the EVM user guide.

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Lucas, 

    Thanks for the reply. Let me confirm with you.

    For question 4, about termination scheme, is p.58-59 of datasheet you're saying? 

    https://www.tij.co.jp/jp/lit/ds/symlink/dp83td510e.pdf#page=58

    For question 4, about MDI line impedance control, I see p.19 of EVM manual used 50 ohm for impedance control, why is it different from 100 ohm, what you mentioned?

    https://www.tij.co.jp/jp/lit/ug/snlu271a/snlu271a.pdf#page=19

    4. The termination scheme should be in the datasheet. They may refer to the EVM as a full PCB example. Yes, the MDI lines should be impedance controlled with a 100 ohm differential impedance.

    For question 6, sorry I'm not quite understanding what customer meant. Is p.19 of EVM manual what you're talking about?
     https://www.tij.co.jp/jp/lit/ug/snlu271a/snlu271a.pdf#page=19

    6. What configuration are you interested in? The EVM should power up without any additional configuration.

    For register question, Is p.13 of EVM manual showing what you said for initial register setting?

    https://www.tij.co.jp/jp/lit/ug/snlu271a/snlu271a.pdf#page=13

    The initial settings are described in the EVM user guide.

    Could you help confirm if my understanding to question 8, 9 is correct or not? 

    I saw SEM team have PoDL use case from following E2E post, could you share it via mail if you are knowing about this?

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1004678/dp83td510e-evm-poe-use-case/3712816?tisearch=e2e-sitesearch&keymatch=poe%20podl#3712816

    For question 8, I think DP83TD510E do support supplying and receiving power, but TI have no PSE/PD solution for SPE now, is my understanding correct?

    For questions 9, yes, I meant PoDL. Customer is wondering how can SPE superimpose power to data line if they use capacitor instead of transformer for isolation. I think "PoDL Example" in p.2 of following material is showing this, achieved by PSE/PD before capacitor. Is my understanding correct? 

    https://www.tij.co.jp/jp/lit/wp/snla360/snla360.pdf

    Thanks.

    Regards,

    Jo

  • Hi Jo,

    4. Yes, these pages are the correct termination schemes. The link you have placed for the controlled impedance is only showing a picture of a schematic. To clarify, the MDI lines should have 100 ohms differential impedance and the MAC lines should have 50 ohm single ended controlled impedance.

    6. The page you have linked show the different bootstrap options. Additional configurations for setting the PHY post startup (switching between RMII master and slave for example) are described elsewhere in the user guide.

    I'll reach out via email for your questions regarding PoDL.

    Thanks,

    Lucas

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).