This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83TC811R-Q1: power down by register

Part Number: DP83TC811R-Q1

Dear team,

My customer asks me whether we can use register to power down our device. I found that our 0x00 bit[11]=1 means IEEE power down. I don't understand what is the difference between IEEE power down and our power down state described in 8.4.1 sector. Could you please help explain this difference?

Thanks & Best Regards,

Sherry

  • Hello Sherry, 

    Thank you for the query.

    IEEE power down allows access to registers during power down. 

    The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. To control the power down mechanism, this bit is OR'ed with the input from the INT/PWDN_N pin. When the active low INT/PWDN_N is asserted, this bit is set.

    The 8.4.1 is a power down due to the supply threshold and the device will restart including register reset after the power supply becomes normal.

    If there is a specific use case i can provide more details.

    Regards,

    Sreenivasa

  • Hi Sreenivasa,

    Thanks for your reply!

    My customer feedbacks that there is one test item, and they need to control our device power on and power off. From hardware aspect, they can control EN pin. They want to know whether they can control this by software. So I want to know the difference between IEEE power down and our power down state described in 8.4.1 sector. If we use EN pin to power down our device, our device will enter into the power down state described in 8.4.1 sector, and we can't access to registers. If we power down our device by set IEEE power down bit, our device won't reset the register when clearing this bit, right?

    Thanks & Best Regards,

    Sherry

  • Hello Sherry, 

    Thank you for the inputs.

    Please check is customer could use the below register

    Table 43. PHYRCR Field Descriptions

    Regards,

    Sreenivasa