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[FAQ] DS90UB940-Q1: link error meaning

Part Number: DS90UB940-Q1

Hi experts,

1. 940 has link error counter which can monitor link error number. Could you please help to explain what kind of error can be taken as a link error? Datasheet states clk0,
clk1 and DCA are monitored for link errors but can you explain the meaning in details? Do you recommend to enable link error count for mass production project? If yes, what value do you suggest?

2. About 940 PASS pin. What kind of error will be reflected on PASS pin? Datasheet states DE or Vsync length value mismatch. Could you please give more explaination about how PASS pin works?T

Thank you

Arie

  • Hi Arie, 

    1. 940 has link error counter which can monitor link error number. Could you please help to explain what kind of error can be taken as a link error? Datasheet states clk0,
    clk1 and DCA are monitored for link errors but can you explain the meaning in details? Do you recommend to enable link error count for mass production project? If yes, what value do you suggest?

    CLK0/1 are extra bits at the beginning/end of each data frame that are used for clock recovery and encoding. DCA is an additional bit in the frame that combines sequentially to create a 130-bit field containing encoding information.

    At a basic level, the link error counter uses those fields and detects errors in the link.

    I personally don't have any anecdotal data-points on typical production settings for this feature. I will ask other colleagues internally and get back to you. I think it would depend on the error susceptibility of the link and desired system robustness. Either way, it can be used in development/evaluation to help benchmark and bring up the system. 

    2. About 940 PASS pin. What kind of error will be reflected on PASS pin? Datasheet states DE or Vsync length value mismatch. Could you please give more explaination about how PASS pin works?T

    The pass pin will have different operation depending on whether its in its normal operational mode or in BIST mode. 

    For pass, in Normal mode status output pin (BISTEN = 0)

    PASS = 1: No fault detected on input display timing

    PASS = 0: Indicates an error condition or corruption in display timing, meaning DE length value mismatch measured once in succession or VSync length value mismatch measured twice in succession.

    For BIST mode, the pass pin can be monitored to show a frame by frame error flag, allowing to measure a payload error rate of the link. 

    Regards, 

    Logan

    Edit: Reworded/corrected DCA, CLK0/1 explanation. 

  • Hi Logan,

    Could you please give more explaination about how DCA works? Thank you.

    Arie

  • Hi Logan,

    Add one question.

    1. You mentioned "DCA is an additional bit in the frame that combines sequentially to create a 130-bit field containing HS, VS, and DE transitions, locking and data-path control, etc." For 94x, it should be 35 bits, right? From my understanding, the control singal should be contained in other bits, not the DCA bit. Below picture is what I captured from an old training material, could you please help to check if it is correct? What's the meaning of DCA and DCB?Could you please help to give more explaination about how DCA/DCB works?

    2. For the link error count register, when the link error reaches the configured value, will the counter reset to 0?

    BR,

    Arie 

  • Hi Arie, 

    For 94x, it should be 35 bits, right?

    No, the 35-bits is the payload frame. The DCA and DCB field is one bit in that larger 35-bit frame that combines sequentially to generate a 130-bit field which has additional control information. 

    For the link error count register, when the link error reaches the configured value, will the counter reset to 0?

    When the threshold is met, the link will lose lock. The register in question, presumably 0x41[3-0], is only the threshold level, not the error count itself. There is no way to view the current count of link errors

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your information.

    1. For DCA, please check if my understanding is correct: since there is one DCA bit in one pixel, there will be many DCA bits in one frame, those DCA bits generate a 130-bit field containing HS, VS, and DE transitions, locking and data-path control, etc. Is that right? So if there's a link error, it could be related to HS, VS, DE mismatch, right?

    2. What's the difference between DCA and DCB?

    3. For the link error count, I think there should be a counter inside the chip. For example, if I set the threshold to 8 errors, the counter will count the error, when the error reaches 8, then the link will lose Lock and AEQ starts. After that, will the counter reset to 0? Or the counter will keep counting?

    BR,

    Arie

  • Hi Arie, 

    I misworded an earlier reply that might be causing some confusion. 

    Let me elaborate: 

    The FPD-Link protocol creates packets (frames) to send over the high speed forward channel. These packets contain video data, clock bits, and other data including encoding bits. In this case the 940 packet structure contains 2 clocking bits per frame and a DCA bit which is for FPD-Link encoding. When each packet is received these specific bits can be checked against their expected value and if there is not a match, then an error will be flagged. 

    The HS, VS, and DE transition mismatch is indicated by the PASS pin specifically, not the link error flag. 

    3. For the link error count, I think there should be a counter inside the chip. For example, if I set the threshold to 8 errors, the counter will count the error, when the error reaches 8, then the link will lose Lock and AEQ starts. After that, will the counter reset to 0? Or the counter will keep counting?

    The counter should reset after a reset or a successful re-lock.

    Regards, 

    Logan