DS110DF111: Step to configure the CTLE function

Tess Chen

Part Number: DS110DF111

Hi team,

We fail to configure DS110DF111 with CTLE function.

1. Based our understanding is that the CTLE is divided into 15 step and is selected through the register 39. But the selection is not responsive. Do you have any guide for us for the register configuration to enable CTLE function?

2. The chip has four modes (setting the adaptation/lock mode), how do I configure for different mode?

Thanks a lot for the help. Thanks.

Best Regards,

Tess Chen

over 2 years ago

0 Rodrigo Natal over 2 years ago

TI__Mastermind 19135 points

Hi,

Please refer to the 10G retimer programming guide per link below for details.

https://www.ti.com/lit/an/snla323/snla323.pdf

Typically you should not need to configure the CTLE boost vmanually. Instead you may rely on one of the automatic Rx EQ adapt modes. The adapt mode is set via channel register 0x31. Refer to the above linked programming guide for full instructions and details.

Regards,

Rodrigo Natal

HSSC Applications Engineer

0 Tess Chen over 2 years ago in reply to Rodrigo Natal

TI__Intellectual 2675 points

Hi Rodrigo,

We still could not make it work even according to the https://www.ti.com/lit/an/snla323/snla323.pdf. Could you give the mandatory configuration steps for CTLE function? Thanks a lot.

Best Regards,

Tess Chen

0 Rodrigo Natal over 2 years ago in reply to Tess Chen

TI__Mastermind 19135 points

Hi Tess,

What retimer input signal data rate and pattern is being used?
Can you provide a full channel registers dump for when you are seeing the issue?

Thanks,

Rodrigo

0 Tess Chen over 2 years ago in reply to Rodrigo Natal

TI__Intellectual 2675 points

Hi Natal,

1. The input data rate is 9.953Gbps，and pattern is Prbs31.

2. Please see the below registers dump.

DS110DF111EVMData.ini

0 Rodrigo Natal over 2 years ago in reply to Tess Chen

TI__Mastermind 19135 points

Hi Tess, see my feedback below related to the shared retimer register dump values,

Channel A
- Shows no input signal detected. Hence no CDR lock
Channel B
- Shows channel register 0x02 = 0xDC.This means that signal was detected and CDR was successfully locked
- Eye opening values
  - 0x27 = 0x35. This means horizontal eye opening (HEO) = 0.82UI
  - 0x28 = 0x90. This means that vertical eye opening (VEO) = 450mV
  - Conclusion: Eye opening values are excellen

Overall, channel B looks good while channel A does not have input signal. Please provide input signal to channel A

Thanks,

Rodrigo Natal

0 Tess Chen over 2 years ago in reply to Rodrigo Natal

TI__Intellectual 2675 points

Hi Rodrigo,

Thanks for checking the register map. DR、DFE、VOD functions are bale to achieve. We are trying to enable CTLE function to see different result for eyes but see no changes even according to the programming guide. For this special function, could you help clarify a little bit about the configuration steps?

Tess

0 Rodrigo Natal over 2 years ago in reply to Tess Chen

TI__Mastermind 19135 points

Hi,

To configure CTLE manually:

Set channel register 0x2D[3]=1
Enter the desired CTLE value via channel register 0x03

Thanks,

Rodrigo Natal

Interface

Interface forum

DS110DF111: Step to configure the CTLE function