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Original question:

DP83TG720S-Q1: DP83TG720S-Q1 loopback

DP83TG720S-Q1: loopback not work

Hung Vu
Prodigy 30 points
Part Number: DP83TG720S-Q1

Hi ,

I am bringing-up DP83TG720S with Rcar H3 chip via RGMII in android 9. I referred driver for DP83TG720S at https://www.ti.com/tool/ETHERNET-SW. After adding driver, PHY linux layer adopted DP83TG720S PHY but when I try to test Digital loopback mode, all RX packets is automatically generated from PHY sent to MAC are error. When dumping pulse on RX_* pin, I saw that, RX_CTRL is always HIGH as in frames and LOW as in inter-frames. This identicates "Data Reception with Errors" but i don't know the root cause of this issue.

All register i set for Digital loopback with data generator and checker (referring to page 31: DP83TG720S-Q1 Datasheet SNLS604D – SEPTEMBER 2020 – REVISED MARCH 2021):

ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x16, 0x4);
ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x800, 0x800);
ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x0619, 0x1555);
ret = phy_write_mmd(phydev, DP83720_DEVADDR, 0x0624, 0x55BF);

Please give me some advice !

 

  • 0
    TI__Genius 16025 points

    Hello Hung,

    After enabling digital loopback, do you see register 0x0001 becoming 0x0145 (link-up indication)? After writting the registers, are you able to read the written registers back correctly? Also what do you read when you read 0x063C, 0x063D and 0x063E in this sequence after loopback + data-gen/check enable?

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 30 points

    Thank Vikram for your reply. After reading 0x0001, result is 0x0145 , 0x063C and 0x63D  have values > 0 and 0x063E's value = 0. All value seem to be good. There is any clues I can debug to solve this issue from here.

  • 0 in reply to Hung Vu
    TI__Genius 16025 points

    Hello Hung,

    Rx_Cntrl will be high for full frame without errors and all the health checks inside the PHY of the datapath is looking fine, so there are no errors in data coming out of PHY. May be there is a problem in Rgmii interface between MAC and PHY. Do you have capability to send data from MAC and check if correct data is coming back to MAC by enabling Rgmii loopback of the PHY. This will only test Rgmii interface and point out the problem here. Also make sure that correct Rgmii mode is selected in MAC side and PHY side (Rgmii align in MAC + Shift in PHY or Rgmii shift in MAC + Rgmii align in PHY).

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 30 points

    Thank Vikram, 

    RGMII loopback mode does not works also, I am selecting RGMII TX internal delay  mode on MAC, so I set 0x0602 register to 0x0001, that's right ? And I have a big question, Does MAC need to read RGMII In-Band Status(Duplex statues, CLK clock speed,...) from PHY first to setting itself before MAC can send TX packets to PHY ? Sorry, it is maybe a basic question because I'm newbie in this field. I have just measure clock speed on TX_CLK, it is just 25MHz, not 125MHz. The problem may be there.

  • +1 in reply to Hung Vu
    Prodigy 30 points

    After tracing PHY framework source code in Linux. I saw that PHY driver can not run into PHY_RUNNING mode because aneg_complete bit in BMSR register is not set. So, I tried faking aneg_complete bit to 1, and setting clock speed to 1000 and mode to Full Duplex in my driver. Now TX packets can be transmitted to PHY with 125MHz clock speed and send back on RX_* data line.